Randy Thomas work email
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Randy Thomas personal email
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• Seeking 90% remote physical design positions (RTL to GDS2). Please, no 100% RTL coding or verification positions.• Expert with the latest EDA tools; expert with Synopsys, Cadence, Mentor Calibre, Apache, Ansys.• Up-to-date with the entire SoC/ASIC/ASSP physical design from RTL to GDS2: architecture and circuit design, IP selection and validation, constraint development and verification, early prototyping to select process and cell libraries for optimal PPA, pad-ring and power grid design, DFT, synthesis, place and route, formal verification, SI/EM/IR/noise analysis and mitigation, high-speed interfaces, CTS, MMMC STA and timing closure, SI/IR/EM/DRC/LVS/DFM, nano CMOS (5nm, 10nm, 16nm, 22nm, 28nm, 40nm, 55nm, 90nm), package design, flip-chip & area I/O.• Demonstrated ability to create, optimize, and automate tools and design flows using TCL, Python, Perl, Make, YAML, & BASH.• Experienced at training new team members and leading by example. Demonstrated ability to work well as an independent self-starter or as part of a large or small multidisciplinary team.• Highly skilled at many traditional and innovative low-power design methodologies and power intent (UPF/CPF): clock and power gating, data retention, isolation and level-shifter cells, dynamic and adaptive voltage and frequency scaling (DVFS, AVFS), multi-Vt/multi-height cells, pulsed-latch clocking, power synthesis, analysis, and optimization, POR core creation and validation, and meaningful early-stage power analysis.• Strong verbal and written communication skills; experienced with and managing large and geographically/culturally diverse teams on large-scale projects with strict schedules and limited resources.• Lead engineer supporting sales and marketing design-win efforts for high-profile multi-million-dollar projects. • Experienced project manager: schedule management and tracking, risk analysis, and mitigation.• Ongoing training with Siemens Tessent DFT, Synopsys Fusion Compiler, Synopsys.ai, and Cadence JedAI tools to leverage AI and Machine Learning in VLSI development and DFT tools.• Expert in Verilog, UNIX/Linux, Perl, TCL, Python, DFT, MBIST, LogicBIST, ICC2, Design Compiler, Power Compiler, Genus, Fusion Compiler, Innovus/DDI, Conformal/Litmus, CDC/RDC, VCS, NCVerilog (IUS), Xcellium, Formality, STA, power analysis (Voltus, Joules, PrimePower, PowerPro, PowerArtist), Calibre and Pegasus DRC and LVS, HSPICE, Git, Collabra, Jira, Slack, MS Office, Visio, Teams, and many other tools.• Experienced on both sides of IP development and implementation: as a vendor and a customer.
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OwnerRanomco Holdings LlcBoston, Ma, Us -
Asic/Soc/Ip/Eda Automation Senior Design EngineerIntel Corporation Jun 2024 - PresentSanta Clara, California, Us• Responsible for automating IP verification flow including support for a vast array of internal and 3rd party EDA design tools.• Converted flow requiring 144 files (each of which included dozens of hard-coded paths and settings), ~8,000 lines of code, and brute-force 1-2 hour delays between job stages into three (3) files, only one of which requires editing to set paths/preferences and fewer than 2,000 lines of code.• Typical run time for total flow reduced from ~12 hours to ~4 hours.• Added robust error checking and email notification of any errors immediately upon detection. -
OwnerRanomco Holdings Llc Jun 2017 - Present• Acted as a task-specific ASIC/SoC design consultant for various companies suffering from schedule risks and/or talent shortages to ensure on-time, first-pass success tape out, test debug, ES evaluation, documentation, and system integration.• Reviewed project requirements, current issues, planned workflows, and evaluated client time and budget constraints. • Prepared original and relevant process, tool, and IP options for clients based on design requirements, schedule, and resource availability. • Helped select process, architecture, package, CPU cores, design flows, vendors, and IP based on project needs.• Provided engineering consulting contract services such as: o Created, automated, and executed flows from RTL netlist to GDSII including synthesis, DFT, place & route, STA, DFM, DRC, LVS, ERC, and all required sign-off checks. o Performed parasitic extraction and MMMC STA, SSTA, and PSTA timing closure. o Employed Formal Verification and CDC/RDC analysis tools to ensure functionality. o Executed Calibre DRC/LVS verification to ensure design rules were met. o Verified IP and design block quality assurance checks to ensure smooth integration and verification.
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Asic Physical Design EngineerLockheed Martin Aug 2023 - Dec 2023Bethesda, Md, Us• Created, implemented, tested, and verified full back-end design flow using Cadence tools (Genus/Innovus/etc.).• Implemented multiple blocks and chip top level using Fusion Compiler to compare PPA results to Cadence.• Completed full mixed-signal simulation using Cadence ADE-L / XCELLIUM.• DRC/LVS using both Pegasus and Calibre.• LINT/CDC/RDC/SDC analysis and consistency check using Cadence Litmus and Jasper Gold.• Worked closely with RTL developers, analog designers, verification, and other teams to coordinate design efforts and ensure constraints were met. -
Asic / Soc Physical Design EngineerInnophase Iot Aug 2022 - Jun 2023San Jose, Ca, Us• Lead engineer responsible for the implementation of a complex, low-power ASIC from RTL to GDS2 using the Cadence Innovus/DDI tool suite (Genus synthesis, Innovus place and route, Tempus STA, Voltus IR drop, Quantus extraction, Joules power, and Pegasus DRC/LVS, as well as Calibre DRC/LVS.)• Executed synthesis and HSPICE analysis of various standard-cell libraries to compare power, performance, and area (including 5nm, 10nm finFET, 16/12nm finFET, 22nm, and 28nm of multiple grid heights and Vt from TSMC, ARM, and Artisan.• Performed lint, SDC, CPF, CDC, and RDC checks using Cadence Jasper, Conformal Litmus, and Conformal Low Power, ensuring the quality and consistency of the design. Provided detailed feedback to the RTL and verification teams to ensure timing closure.• Managed a complex design including an ARM core, a RISC-V core, various IO subsystems, mixed signal and analog blocks, and digital logic blocks in multiple power domains with different libraries and voltages, employing a range of low-power methodologies.• Collaborated with the RTL team to evaluate RTL quality, offering valuable insights and recommendations to enhance timing, area, power, SDC constraint quality and coverage, and clock- and reset-domain crossing (CDC, RDC) synchronization strategies.• Developed TCL, YAML, Perl, Python, Makefile, and BASH automation scripts/files for library loading (including MMMC), design parameter settings, design flow steps, and custom design-specific procedures, automating and streamlining the design process.• Leveraged advanced scripting and design-flow automation to optimize and parallelize the design flow, increasing team efficiency and productivity.• Demonstrated expertise in TCL, Perl, Python, YAML, Make, Verilog/SystemVerilog, Stylus Common UI, BASH, and Linux.• Collaborated with EDA tool, library, and IP vendors to troubleshoot and fix issues.• Clearly communicated design status, open issues, risks, and mitigation plans to the teams and management. -
Principal System Design EngineerYoubiq Inc Aug 2016 - Aug 2022Northampton, Ma, Us• Led engineering design, development, analysis, and simulation of prototypes and 3D computer models for a novel robotic system. Details can be discussed in person as required.• Developed, prototyped, and verified the robotic hardware, API, and embedded software for automated capture and publishing of 360° x 360° panoramic canvases for augmented and virtual reality. -
Senior Staff Design Engineer And Project ManagerRenesas Electronics America Apr 2010 - Apr 2016Koto-Ku, Toyosu, Tokyo, Jp• Project management and ASIC design from RTL to GDS2: Verilog RTL and constraint development and verification, DFT, logic/memory BIST, JTAG, ATPG, formal verification, synthesis/physical synthesis, floor-planning and prototyping (hierarchical and flat,) placement, routing, clock distribution (mesh and CTS,), RC extraction, delay calculation, STA / timing closure, signal integrity, power analysis, DRC/LVS, DFM, ESD, EMI, EMC, package design, ATE interface, and failure analysis for a variety of chip architectures and I/O including DSP, FFT, USB2/3, PCIe, SerDes, (LP)DDR, ECC, ARM, X-bar. • Created a detailed project plan, including defining project scope, objectives, timelines, and resource requirements. • Led and managed a geographically- and culturally-diverse team of semiconductor design engineers across multiple time zones. • Managed the project budget, tracked expenses, and ensured that the project stayed within the allocated financial resources. • Identified potential technical and schedule risks and developed strategies to mitigate them. Conducted risk assessments, proactively addressed any issues that arose, and developed contingency plans to minimize project disruptions or schedule impact. • Acted as the primary point of contact for stakeholders, including clients, executives, and other project team members. Provided regular updates on project progress, managed expectations, and addressed any concerns or issues raised by stakeholders. • Ensured the quality and reliability of the designs by establishing quality assurance processes, conducting regular design reviews, and implementing testing procedures. • Schedule Management: Created, monitored and controlled the project schedule. Tracked action items, milestones, identified and mitigated potential delays or bottlenecks. • Documentation and Reporting: Maintained accurate project documentation, including design specifications, progress reports, and meeting minutes. (truncated for LinkedIn) -
Senior Staff Design EngineerNec Electronics America Aug 1997 - Apr 2010Kawasaki, Kanagawa, JpSimilar roles and responsibilities as at Renesas (above), but less project management.ASIC design from RTL to GDS2: Verilog RTL and constraint development and verification, DFT, logic/memory BIST, JTAG, ATPG, formal verification, synthesis/physical synthesis, floor-planning and prototyping (hierarchical and flat,) placement, routing, clock distribution (mesh and CTS,), RC extraction, delay calculation, STA / timing closure, signal integrity, power analysis, DRC/LVS, DFM, package design, ATE interface, and failure analysis for a variety of chip architectures and I/O including DSP, FFT, USB2/3, PCIe, SerDes, (LP)DDR, ECC, ARM, X-bar.(NEC Electronics and Renesas Technologies merged April 2010.) -
Coop DesignerLockheed Martin Aug 1996 - Aug 1997Bethesda, Md, UsCooperative designer with UF/Lockheed Martin Interdisciplinary Product and Process Design Program. Designed and built prototypes of a Sun S-Bus-to-PCI interface for use with Lockheed Martin's Common-Image Signal Processing (CISP) system. Included printed-circuit board (PCB) design, VHDL creation and FPGA implementation, documentation, manufacturing analysis and prototype creation and system verification.
Randy Thomas Skills
Randy Thomas Education Details
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University Of FloridaElectrical Engineering
Frequently Asked Questions about Randy Thomas
What company does Randy Thomas work for?
Randy Thomas works for Ranomco Holdings Llc
What is Randy Thomas's role at the current company?
Randy Thomas's current role is Owner.
What is Randy Thomas's email address?
Randy Thomas's email address is ra****@****ail.com
What schools did Randy Thomas attend?
Randy Thomas attended University Of Florida.
What are some of Randy Thomas's interests?
Randy Thomas has interest in Mathematics, Programming, Semiconductors, Physics, Skiing, Gardening, Economic Empowerment, Politics, Education, Science And Technology.
What skills is Randy Thomas known for?
Randy Thomas has skills like Semiconductors, Asic, Dft, International Project Management, Clock Tree Synthesis, Physical Design, Timing Closure, Static Timing Analysis, Power Analysis, Physical Verification, Parasitic Extraction, Cad/cam.
Who are Randy Thomas's colleagues?
Randy Thomas's colleagues are Mauricio Aguero, Joe English, Ananth S, Shlomi Haliva, Raghupathy Raja Arumugam, Adam Gaboury, Rebecca Barron.
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