Vlsi Design Engineer
Current•Microarchitecture, RTL implementation & Documentation of several blocks from scratch & re-design. Including programming model definitions.Full flow design in Verilog, Lint, CDC, verification support (Cadence Simvision) & integration. •RTL legacy blocks enhancements•Full PHY integrator with synthesis ramp-up & flow.•Working closely with other VLSI teams - architecture, verification, DFT, FPGA, BE, on site & abroad.