• Designing Skills: Analog circuits, CAD Schematic Capture, Signal integrity, Layout Design, Spice design and simulations, Place & Route, PCB Fabrication.• Testing Skills: Oscilloscopes, Spectrum Analyzers, Network Analyzers, Signal Generators• Tools: ADS, Cadence Virtuoso, Ansoft HFSS, FEKO, Mentor Graphics, Expedition, PADS• Language Known: C, C++, MATLAB, Verilog
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Rfic Design EngineerQualcomm May 2019 - PresentSan Diego, Ca, Us -
Staff Research AssociateNevis Laboratories, Columbia University Aug 2018 - Present
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Rf Systems R&D InternInterdigital, Inc. Sep 2017 - Aug 2018Wilmington, De, Us -
Rfic Design InternAnokiwave May 2017 - Aug 2017Greensboro, North Carolina, Us• Designed a 24G-40G UWB driver amplifier in 45nm RF SOI technology in Cadence Virtuoso and simulated with Spectre RF for mm-wave applications • Implemented with stacked-FET topology to meet the specifications of 20dB gain, OP1dB 15dBm, OIP3 greater than 25dBm. • Automation of test plan for phased arrays in Python scripting. -
EngineerQualcomm Nov 2014 - Jul 2016San Diego, Ca, Us● Understand phone design cycle and risks in current or upcoming ICs.● Interact with various teams such as software, IC, component, testing etc.● Link budget calculation, component selection, characterization, and validation.● Create schematics and PCB design for latest Qualcomm products.● Optimize power amplifier supply voltage for better efficiency and linearity.● Improve RF performance through RF station and device calibration.● Tx/Rx system performance analysis, optimization, debugging and data collection.● Experience interacting with factory to resolve test and performance issues.● Provide detailed technical analysis and resolution of customers’ issues.● Involve in hands-on lab activities. Solid understanding of RF test equipment.● Expertise in cellular technologies like GSM, WCDMA, CDMA, LTE standards. -
Associate EngineerQualcomm Jul 2013 - Oct 2014San Diego, Ca, Us -
Research AssociateCsir-Ceeri Jan 2013 - Jun 2013Pilani, Rajasthan, InHardware Implementation of Pulse Discrete Cosine Transform for Saliency-based videocompression process . Designing the DCT block using the novel approach of NEDA (NewDA) architecture, a low power architecture for DCT based on Distributed Arithmeticapproach favoring additions to multiplications. -
Summer InternQualcomm May 2012 - Jul 2012San Diego, Ca, UsEvaluated different vendor’s MIPI front-end switches for insertion loss, isolation and IIP3from 700MHz to 2.5GHz using the RF bench instrument.Performed link budget analysis for the multi-band (GSM/EDGE, CDMA, UMTS, LTE)RF card. Investigated the isolation and desense issues for co-banding frequency.Performed differential impedance matching for LNA to optimize the sensitivity of thephone using Vector Network Analyzer.Reviewed the RF card’s schematic, block diagram, MIPI control logic table. -
Summer InternIndian Institute Of Technology, Delhi May 2011 - Jul 2011New Delhi, InDesigned "Microwave Band Pass Filter" in Waveguiding Structures which find applicationsin telecom deployed on frequency range (2305-2325 MHz) in CST Studio Suite (ElectromagneticField Simulation) , a high Q-filter(sharp cut-off with low loss) with "iris-coupledwaveguide junctions", employing K -inverter. Also designed microstrip patch antennausing Intelli-CAD, Puff and Serenade.
Rupal Gupta Education Details
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Columbia UniversityElectrical And Electronics Engineering -
Indian Institute Of Information Technology AllahabadElectronics And Communications Engineering -
Dav Public School, Kota -
Kendriya VidyalayaHigh School -
Modern School Kota - India
Frequently Asked Questions about Rupal Gupta
What company does Rupal Gupta work for?
Rupal Gupta works for Qualcomm
What is Rupal Gupta's role at the current company?
Rupal Gupta's current role is Qualcomm Atheros.
What schools did Rupal Gupta attend?
Rupal Gupta attended Columbia University, Indian Institute Of Information Technology Allahabad, Dav Public School, Kota, Kendriya Vidyalaya, Modern School Kota - India.
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