Rupal Jain Email and Phone Number
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An accomplished Technical Program Manager in Cloud Datacenter Efficiency improvement and Consumer Hardware development. I have proven experience delivering results on programs that span on a broad scope of technology architecture, process improvement, and integration engineering. An excellent team player with strong sense of focus and attention to detail while delivering high quality, cost effective products on time.
- Website:
- google.com
- Employees:
- 1
- Company phone:
- 916.253.7820
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Technical Program Manager - Google CloudGoogle Dec 2021 - PresentMountain View, Ca, UsFocusing on programs to increase efficiency and utilization of Datacenters. -
Technical Program Manager - Google DevicesGoogle Sep 2018 - Nov 2021Mountain View, Ca, Us• Worked on diverse portfolio of hardware consumer products (Pixelbuds, Pixel 5/6/6Pro Phone). • Responsible for managing the delivery of sub-system modules (Camera, Display, Coverglass, Battery, SoC, Audio, FPC, PCB etc.), which meet engineering & quality specs. • Closely worked with supplier development engineers to enable new processes, qualify new suppliers, resolve yield issues, improve efficiency, use sustainable materials. Ensure supplier MP line readiness and schedule to meet volume forecast.• Partner & collaborate with cross-functional teams (product, engineering, materials, reliability, operations) to identify risks, dependencies, and actions to work on complex problems for the given product.• Drove products from prototyping to large-scale manufacturing.• Leveraged my engineering experience for complex problem solving and proactively understood the risks/challenges to unblock mass production and timely product launch.• Responsible for communication to different teams, forums, and delivering executive updates. -
Product Integration Manager - Silicon Photonics OperationsIntel Corporation Feb 2016 - Aug 2018Santa Clara, California, Us• Worked with cross-functional teams and stakeholders on Silicon Photonics 3D SIP (System-in-Package) for 400Gbps product, overseeing design, assembly processes, materials, DFM (design for manufacturing), reliability, and high-volume-manufacturing.• Partnered with OSATs for ASIC package development from concept to manufacturing.• Drove ODM/OEM for product NPI line bring-up, ramp up, and streamlining operations through production including manufacturing process control.• Designed and implemented capacity planning model for HVM capacity analysis and effective decision making on 100G optics product. -
Assembly Packaging R&D EngineerIntel Corporation Oct 2012 - Jan 2016Santa Clara, California, Us• Simultaneously drove 9 products (14nm Broadwell/ Skylake EP Xeon) to HVM. Responsible for NPI planning, execution, material/process selection-development-optimization, reliability assessment, failure analysis, product certification, and building engineering/pre-production/customer samples.• Ran Design of Experiments (DOE) of module teams followed by extensive data and failure analysis.• Successfully delivered and certified novel 2.5D server process technology with approximately $120M savings from assembly cost compared to traditional packages. The process development involved first-of-a-kind tools install/qual, new materials, assembly processes, and integrated automation.• Designed first-of-a-kind assembly process flow for this novel process technology with >50 steps by effectively collaborating and integrating various module teams and led to successful NPI execution. -
Senior Process Technology Development EngineerIntel Corporation Oct 2007 - Sep 2012Santa Clara, California, Us• Extensive hands-on assembly floor experience. Responsible for stable and capable process development of chip attach process, which included materials selection and flip-chip solder attach• Strong knowledge & experience with Six Sigma, Statistical Process Control (SPC) methodologies, and statistical software (JMP). Responsible for establishing and maintaining process controls and monitors to ensure in-situ stable process performance to achieve assembly yields >99%. -
Graduate Research AssistantUniversity Of Maryland Aug 2005 - Sep 2007College Park, Md, Us• Design and fabrication of a bio-inspired MEMS iron-gallium nanowire acoustic sensor for underwater applications. Fabrication, testing, and modeling (FEA) of micromembranes using laser vibrometer.• Evaluated acoustic impedance of polymer encapsulation materials using scanning acoustic microscopy.• Investigated acoustic performance of different encapsulation materials and filler fluids for the nanowire acoustic sensor package. -
Automative EngineerTata Motors Jul 2004 - Jul 2005Pune, Maharashtra, In
Rupal Jain Skills
Rupal Jain Education Details
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University Of MarylandMechanical Engineering -
G. B. Pant University Of Agriculture & TechnologyMechanical Engineering
Frequently Asked Questions about Rupal Jain
What company does Rupal Jain work for?
Rupal Jain works for Google
What is Rupal Jain's role at the current company?
Rupal Jain's current role is Technical Program Manager - Google Hardware.
What is Rupal Jain's email address?
Rupal Jain's email address is ru****@****ail.com
What is Rupal Jain's direct phone number?
Rupal Jain's direct phone number is (410) 706*****
What schools did Rupal Jain attend?
Rupal Jain attended University Of Maryland, G. B. Pant University Of Agriculture & Technology.
What are some of Rupal Jain's interests?
Rupal Jain has interest in Indian Institute Of Technology, Maharashtra, India, Avanti Fellows, Bombay, Bain And Company, Mumbai.
What skills is Rupal Jain known for?
Rupal Jain has skills like Management Consulting, Analytics, Data Analysis, Business Strategy, Strategy, Financial Modeling, Private Equity, Valuation, Business Development, Business Analysis, Due Diligence, Corporate Finance.
Who are Rupal Jain's colleagues?
Rupal Jain's colleagues are Yeung Pang, Maxim Getman, Nikola Lukic, Wesley Bierhalter, Sebastien Pineau, Onj Hin, Nan W..
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