Rupesh Patil Email & Phone Number

A design verification engineer with 5+ years of experience in verification using System Verlog and UVM. Working on verification of 64 port network switch used for HPC applications. Worked on module level and SoC level testbenches for next generation eSSD memory controllers. Graduated from San Jose State University with MS degree in Electrical Engineering, possess strong interpersonal and problem solving skill. I am a dedicated team player and have collaborated with cross functional teams across different geographies to meet the project milestones. Skills:Technical skills : RTL verification, with System Verilog and UVM, Assertions, Functional Coverage, Platforms : Linux (Fedora), WindowsProgramming languages : System Verilog, Verilog, Python, Embedded C, C/C++, VHDL, assembly.Communication Protocols : AXI, AHB, APB, I2C, SMBUSEDA Tools : Cadence Xcelium, Cadence IMC, Synopsys Design Compiler, Synopsys VCS, Cadence Vamanger

Listed skills include System On A Chip, Computer Architecture, C, Very Large Scale Integration, and 18 others.