Leading the Digital design team responsible for High-speed serial links Phys, controller and sub-system for sensors, Data convertors (ADC and DAC), Memory BIST and Repair solution. - 19+ years of experience in RTL Design and Architecture of Digital IPs. - 25+ filed and granted patents - Strong knowledge of ASIC design flow- Hands on High Speed Digital Design, covering all aspects of front end design (Design Specification & Architecture , RTL coding, verification, DFT, synthesis, timing and power analysis).- Support for post silicon validation - MATLAB Modeling- HDL modeling of analog and digital IPs. - Good exposure of High Speed Links Physical Layer