Rutuja Gogulwar Email & Phone Number

▪︎ 3+ years of experience as an ASIC RTL Engineer, specializing in RTL design and Tool Flow Methodology (TFM) implementation.▪︎ Hands-on experience with RTL coding using Verilog and SystemVerilog.▪︎ Expertise in tool flow setup and enablement, supporting RTL design flows and ensuring tool compatibility.▪︎ Proficient in RTL static check tools including Spyglass (Lint, CDC, DFT), VC Lint, VC LP, Collage, Defacto, and Fishtail.▪︎ Extensive experience with synthesis tools like Fusion Compiler and other backend flows like Logic Equivalence Checking (LEC), Caliber, and SAGE ATPG.▪︎ Responsible for violations debug and analysis for RTL front-end static checks, ensuring design quality and integrity.▪︎ Worked on advanced custom flows like R2G lite and Cheetah2, streamlining front-end to back-end handoff processes.▪︎ Strong ability to collaborate with cross-functional teams and work for high-profile clients like Intel.▪︎ Actively seeking opportunities to apply my RTL design expertise and contribute to innovative, cutting-edge projects.