Robert Woods-Corwin Email & Phone Number

ASIC Verification:Designed a verification architecture using monitors and predictors, in order to efficiently find bugs at the many levels of scale inherent in SoC verification. Verified Level 2 cache segment of multiprocessor ASIC. Also verified cache coherent memory system across multiple design components. Co-designed and implemented a SystemC-based functional coverage collection and reporting tool. See http://www.veripool.org/wiki/covviseSystem Software:Designed cluster management software supporting node boot and configuration, as well as node console and remote kernel gdb for debugging.Developed global clock synchronization software which improves performance on massively parallel applications by synchronizing kernel timer interrupt across the nodes of the cluster.

Verification Engineering on ASIC projects at numerous companies ranging from megaliths like Intel and Sun to tiny startups banking their entire company on the correctness of their first ASIC.Various types of verification work on Verilog and VHDL ASIC designs, ranging from the block-level protocol of LCD controller logic to board-level network processor communications bandwidth analysis.Experience with numerous commercial and open tools and environments; Vera, SystemVerilog, Specman 'e', C, C++, Verilog, VHDL, bash, perl, make...