Ryan Arp Email & Phone Number

San Jose, Ca, Us

Boise, Idaho, Us

• Supported bring up and debug of Micron’s internal SAS controller by leveraging past ASIC RTL and embedded FW experience.• Identified Host RTL and FW issues on internal FPGA platforms, determined workarounds, and validated solutions.• Audited DDR3 and ONFI interface characterization plans, clock tree settings, register values, and programmer’s guide use cases. • Assisted development and qualification of partner SAS drive programs. Debugged drive behavioral, performance, and customer integration issues and worked as a cross functional enabler for internal Micron teams interfacing with the partner company.

Palo Alto, California, Us

ASIC applications engineer supporting cellphone baseband processor development and productization in Broadcom's Mobile and Wireless business unit.Baseband Development Support● Design group liaison supporting pre tape-out and bring-up activities in a multi-faceted role as the baseband expert.● Familiarized with new IP blocks or ASIC functions by reviewing design Verilog/VHDL to support development and customer teams to rapidly resolve issues from baseband bring-up through customer mass production. Understood the baseband functions, blocks, interfaces, power domains, clocking, architectural implementations, and the various hardware platforms. ● Filled the cross-functional knowledge gap between the baseband ASIC and the other phone platform components.● Hands-on hardware and software failure analysis activities with both internal and customer hardware platforms running development software builds or standard Android OS releases. Supported across internal, FAE, and customer groups.● Performed internal and customer training for new basebands, IP blocks, or architectural implementations.● Reviewed and approved baseband characterization plan and assisted in debugging on the bench or in ATE.● Micro-architecture definition and design specification. Device errata, application notes, and technical reports for both internal and end customer audiences. Cross-functional communication between marketing, management, and engineering teams.

San Jose, Ca, Us

Design engineer responsible for disk controller memory interfaces and memory devices across all product platforms as part of the SoC Program Management and Component Engineering unit.Controller Development Support● Led bring up and initial checkout of new all controllers focusing on the memory interfaces and memory technologies.● Directed failure analysis on memory devices and cross-functional controller issues ranging from supplier quality, design flaws, firmware errors, PCBA layout deficiencies, and manufacturing process errors at both the local and global levels.● Authored firmware setting and usage procedure documentation for all memory devices and drive controllers.● Specified the memory device requirements for procurement teams. Worked with both internal design groups and memory device suppliers to define and integrate new features, operating modes, and packages to enhance our products.Component Engineering and Device Qualification● Defined the DDR1/2/3 SDRAM, serial flash, eMMC, and NAND device signal integrity and protocol testing procedures for memory device qualification and distributed them globally to other development and factory teams. ● Constructed, programmed, and maintained the SDRAM, serial flash, eMMC, and NAND test software suite that is used globally for component engineering qualifications and for memory device or controller failure analysis.