Ryan Braid
AeroLeads people directory · profile

Ryan Braid Email & Phone Number

Senior Staff Digital Design Engineer at Lightmatter at Lightmatter
Location: Cambridge, Massachusetts, United States 8 work roles 1 school
1 work email found @lightmatter.ai LinkedIn matched
✓ Verified Jun 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email r****@lightmatter.ai
LinkedIn Profile matched
3 free lookups remaining · No credit card
Current company
Role
Senior Staff Digital Design Engineer at Lightmatter
Location
Cambridge, Massachusetts, United States

Who is Ryan Braid? Overview

A concise factual answer block for searchers comparing this professional profile.

Quick answer

Ryan Braid is listed as Senior Staff Digital Design Engineer at Lightmatter at Lightmatter, based in Cambridge, Massachusetts, United States. AeroLeads shows a work email signal at lightmatter.ai and a matched LinkedIn profile for Ryan Braid.

Ryan Braid previously worked as Senior Staff Digital Design Engineer at Lightmatter and Senior Digital Design Engineer at Lightmatter. Ryan Braid holds Bachelor Of Science (B.S.), Computer Science And Engineering from The University Of Toledo.

Company email context

Email format at Lightmatter

This section adds company-level context without repeating Ryan Braid's masked contact details.

{first}@lightmatter.ai
86% confidence

AeroLeads found 1 current-domain work email signal for Ryan Braid. Compare company email patterns before reaching out.

Profile bio

About Ryan Braid

Experienced ASIC engineer with eleven years experience working with a variety of tools on many different designs and environments.

Listed skills include Verilog, Asic, Rtl Design, Low Power Design, and 43 others.

Current workplace

Ryan Braid's current company

Company context helps verify the profile and gives searchers a useful next step.

Lightmatter
Lightmatter
Senior Staff Digital Design Engineer at Lightmatter
AeroLeads page
8 roles

Ryan Braid work experience

A career timeline built from the work history available for this profile.

Senior Staff Digital Design Engineer

Current

Mountain View, California, US

Apr 2022 - Present

Senior Digital Design Engineer

Mountain View, California, US

Feb 2018 - May 2022

Senior Ip Logic Design Engineer

Santa Clara, California, US

RTL design, IP delivery and support for Atom Based SoCs: •Lead RTL Designer for changes to IA subsystem IPs, including coherent interconnect with support for atom x86 cores, protocol conversion IPs, and legacy IPs including two microcontrollers with subsystem power management control. •Maintain and improve these IPs for features, power, and area. Utilize.

Apr 2014 - Feb 2018

Component Design Engineer

Santa Clara, California, US

  • AXI and OCP Bridge Development:
  • Owned complete RTL design for two highly configurable protocol conversion IPs to translate AXI and OCP to in-house protocol. Implemented out-of-order transaction completions through HW linked list implementation.
  • Designed support for burst transfers and mismatched data-width through Verilog parameterization, reuse of components between the two for simplification of validation, supported CoreKit generation via Synopsys.
  • Responsible for modifications for reuse of Image Signal Processor wrapper used in leading edge Atom SoC product. Included adding new features, as well as driving testplan development for validation of these features.
  • Supported back-end team by providing MCOs and defined timing constraints for this complex design with 17 different clock domains including many full-chip timing arcs.
  • Wrote post-Si python test infrastructure to exhaustively characterize firmware performance for a variety of camera modes and CSI link parameters, as well as modified windows camera driver to debug issues with this IP..
May 2008 - Apr 2014

Undergrad Intern Technical

Santa Clara, California, US

  • Aided in the pre-silicon validation of multiple functional blocks, including a link layer component for CPU interconnect (Quick Path Interconnect), and an XML acceleration engine.
  • Responsibilities included test writing and debug, checker development, functional code coverage writing and filling through constrained random test generation.
May 2007 - Jan 2008

Undergrad Intern Technical

Santa Clara, California, US

May 2006 - Aug 2006

Undergrad Intern Technical

Santa Clara, California, US

Aug 2005 - Jan 2006

Undergrad Intern Technical

Santa Clara, California, US

Jan 2005 - Apr 2005
1 education record

Ryan Braid education

  • The University Of Toledo
    The University Of Toledo
    Computer Science And Engineering
FAQ

Frequently asked questions about Ryan Braid

Quick answers generated from the profile data available on this page.

What company does Ryan Braid work for?

Ryan Braid works for Lightmatter.

What is Ryan Braid's role at Lightmatter?

Ryan Braid is listed as Senior Staff Digital Design Engineer at Lightmatter at Lightmatter.

What is Ryan Braid's email address?

AeroLeads has found 1 work email signal at @lightmatter.ai for Ryan Braid at Lightmatter.

Where is Ryan Braid based?

Ryan Braid is based in Cambridge, Massachusetts, United States while working with Lightmatter.

What companies has Ryan Braid worked for?

Ryan Braid has worked for Lightmatter and Intel Corporation.

How can I contact Ryan Braid?

You can use AeroLeads to view verified contact signals for Ryan Braid at Lightmatter, including work email, phone, and LinkedIn data when available.

What schools did Ryan Braid attend?

Ryan Braid holds Bachelor Of Science (B.S.), Computer Science And Engineering from The University Of Toledo.

What skills is Ryan Braid known for?

Ryan Braid is listed with skills including Verilog, Asic, Rtl Design, Low Power Design, Upf, Soc, Logic Synthesis, and X86.

Find 750M verified contacts

Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.