RTL design, IP delivery and support for Atom Based SoCs: •Lead RTL Designer for changes to IA subsystem IPs, including coherent interconnect with support for atom x86 cores, protocol conversion IPs, and legacy IPs including two microcontrollers with subsystem power management control. •Maintain and improve these IPs for features, power, and area. Utilize UPF additions to add power gating and Dynamic Voltage Scaling. Identify potential issues and recode IPs with synthesis optimization for area and power in mind, as well as improving implicit and explicit clock gating. •Follow subsystem through product lifecycle including pre/post-silicon bringup and debug in a variety of environments and geographies. Includes writing focused x86 assembly and C based tests to validate SoC level interactions between a variety of IPs and the system interconnect, as well as processor and system level power states. Debug of LEC and synthesis issues including standard cell replacement.•Own configuration methodology and TCL automation of larger subsystem connectivity generation via Synopsys DesignWare tool suite. Implemented single configuration file to control the build-time addition and reconfiguration of subsystem IPs based on SoC requirements for quick changes, enabling multi-configuration builds out of a single repository to validate 6 product configurations concurrently.

AXI and OCP Bridge Development: •Owned complete RTL design for two highly configurable protocol conversion IPs to translate AXI and OCP to in-house protocol. Implemented out-of-order transaction completions through HW linked list implementation. •Designed support for burst transfers and mismatched data-width through Verilog parameterization, reuse of components between the two for simplification of validation, supported CoreKit generation via Synopsys CoreTools. Image Signal Processor Integration: •Responsible for modifications for reuse of Image Signal Processor wrapper used in leading edge Atom SoC product. Included adding new features, as well as driving testplan development for validation of these features. •Supported back-end team by providing MCOs and defined timing constraints for this complex design with 17 different clock domains including many full-chip timing arcs. •Wrote post-Si python test infrastructure to exhaustively characterize firmware performance for a variety of camera modes and CSI link parameters, as well as modified windows camera driver to debug issues with this IP. Reduced time from new firmware release to characterization by 100x. System Fabric development and reuse for Atom Based SoCs: •Responsible for git repo management for team, including automation scripts and regression testing. •Owned merge conflict resolution when syncing with other SoC branches as well as testbench conversion to OVM.

•Aided in the pre-silicon validation of multiple functional blocks, including a link layer component for CPU interconnect (Quick Path Interconnect), and an XML acceleration engine. •Responsibilities included test writing and debug, checker development, functional code coverage writing and filling through constrained random test generation.