Ryan Gauthier Email & Phone Number

Boston, MA, US

Hartford, Connecticut, US

Hartford, Connecticut, US

Sunnyvale, California, US

• Contributed to the Design Implementation team during a 12-month contract to take part in the Physical Design of DDR PHYs from RTL to GDS on 7nm technology node projects
• Implemented digital hard macros in DDR PHY IP to align with design rule checks and, through static timing analysis, achieve timing closure according to mathematically-determined constraints
• Maintained design flow and scripts on a block of the design, both independently and with a team, through floorplanning, power grid placement, scm construction, clock tree optimization and synthesis
• Modified scripts to optimize placement and routing of clock trees to minimize clock skew across many flops, while still obeying minimum delay special checks
• Analyzed special timing checks to identify critical paths and carefully engineered a design that successfully complied with various minimum delay, maximum delay, and skew checks
• Utilized PrimeTime in tandem with ICC2 to implement wire and cell edits for timing improvements and DRC fixing to deliver my block as part of a complete project

Sunnyvale, California, US

• Worked with the Verification team to verify DDR Phy IP by doing formal verification using IC Formal
• Optimized the verification environment by restructuring the test flow utilizing shell commands to edit files
• Established push-button flow to test connectivity using formal verification
• Discovered issues and enhanced this push-button flow to expand to more applications

Sunnyvale, California, US

• Worked with the Design Implementation team to create DDR Phy IP
• Prioritized tasks in Excel by tracking metrics of DRCs, electrical checks, and RTL edits
• Debugged and manually fixed sub-micron DRC violations on multiple IP blocks
• Applied skills in ICC2 to make metal edits to resolve physical design issues
• Generated clock diagrams using MS Visio to represent new PHY architecture by reading Verilog RTL
• Wrote Tcl scripts in ICC2 to check pin and macro placement in new design