Ryan Lott Email & Phone Number

Little Rock, Ar, Us

Arlington, Va, Us

Little Rock, Arkansas, Us

Arlington, Va, Us

San Jose, Ca, Us

Develop custom tuning algorithms for Spectra7’s broadband equalizers for active copper cable and backplane channels in the context of the end application e.g. 50GBASE-CR/KR. Develop necessary characterization qualifications for chips and assemble appropriate test plans. Still presently responsible for duties from prior Hardware Design Engineer position at Spectra7.

San Jose, Ca, Us

25+Gbps NRZ and 50+Gbps PAM4 Active Module/PCB/PaddleCard Design (Pre-Layout/Layout/Post-Layout) of standardized copper cable form factors; specifically QSFP, SFP, QSFP-DD to date. Also design standard and custom active hybrid modules containing serial links attributed to USB (480Mbps-10Gbps)/HDMI (3.4Gbps-12Gbps)/DisplayPort (5.4Gbps-8.1Gbps) in support of AR/VR/MR markets.Overseer of physical layer measurement, extraction, budgeting, implementation, and channel analysis for interconnects such as PCB Traces, PCB-Connector Mating Regions, Vias, TwinAx Cable, TwistedPair Cable, MicroCoaxial Cable, Wire Terminations, Packages, IC transfer functions, Coaxial Launches, and the aggregate collective of said elements for various industry standards.

Lisle, Il, Us

Leader in creating new ways to improve lab conditions, providing data collection on 20GHz - 50GHz VNA multiport systems with faster & more accurate methods for massive S-Parameter measurements. Lead SI development teams in acquiring and/or designing analysis techniques that allow tracing root causes for failing interconnect assemblies & providing theoretically backed solutions to overcome them. Managed & developed test plans while ensuring the highest quality standards for over 10 different projects for cable assemblies & associated interconnects from low speed to high speed Ethernet assemblies. Implemented a full scale efficiency study for Multiport VNAs for passive DUTs. Optimized "noise" floor while maintaining linearity at RXs & controlled IF Bandwidths with Segmented Sweeps. As a result, 16 Port sweep speed increased by 300-700% depending on frequency span/step size & up to 3100% if GPIB control was used to reduce measurement to THRUs only.Designed techniques for transforming 2xTHRU Differential Fixture Models to more accurate representations of the PCB DUT Fixture using signal flow diagrams and time domain gating methods.Proposed & implemented correction techniques for extracting DUT attenuation values in the presence of poor port launches & re-reflections. This aided in correlation of bulk cable measurements to modeled data & link budgeting.Developed testing methodologies for non-50ohm DUT/Systems using port renormalization techniques, fixture de-embedding, or gating depending on the necessities of strong accuracy & quantified repeatability.Collected interconnect data and used scripting for machine/data post-processing/report automation. (Python)Developed procedure for testing raw bulk cable that optimized launch impedance discontinuities & reduced asymmetries with false high frequency mode conversion results through analysis of adjacent coupling (NEXT) & SE impedance profiles. Also implemented frequency domain characterization skew techniques.

Lisle, Il, Us

Provided data to design & testing engineers for finished cable assembly designs for protocol interfaces such as SAS, Infiniband, IEEE 802.3, & USB.Designed simple low speed PCBs to complement new cable assembly harness designs.