ProMatch is a volunteer career resource center providing job search workshops and professional networking opportunities in the SF Bay Area.

Performed NAND Flash-storage based systems design, analysis, integration and verification from product definition and planning through production and release. • Analyzed and completed failure analysis dealing with performance, firmware, hardware, or device on 19nm eX2 systems for Liger (WD joint venture) and PPN (Apple). Completed system validation for a SSD (24nm eX3 SATA) project by using logic analyzer traces for regression failure modes and correcting low level sequences.• Improved coverage of low-level sequences by 28% by converting SCAPA, a scripting program to verify sequences against the Livet model, to run on custom in-house testers. Programmed scripts and led a team to complete the total project in 11 months, 1 month ahead of schedule. • Wrote and collaborated on several patents to improve Flash memory cycled data retention performance. • Performed failure analysis on customer returns and worked with a cross functional team in resolving them.• Ensured the iNAND (eMMC) system team received the best optimized memory by negotiating with design and device teams on performance and reliability requirements and writing the Memory Products and Requirement specification.

Product Engineer Manager: Supervised global cross-functional teams from US, Japan, Thailand, and Malaysia, bringing projects to market on schedule and within budget for yield and test times. • Performed product validation by completing the characterization and qualification on multiple new technology nodes. • Collaborated on creating a new automated characterization test suite to enable a more streamlined approach which would pass EVT and PVT. • Led the New Product Introduction for 65nm from a SMIC foundry by collaborating with design, process, manufacturing, test, quality, and marketing from design phase through mass production. Set priority for schedules and initiatives on multiple concurrent projects. • Passed TS16949/QS 9000 audits by creating DFMEAs, root cause analysis, and after action reports summarizing lesson learned.Supervisor Product Engineer: Project leader on yield analysis, test time reduction, characterization and qualification to ensure that products meet datasheet specs and lifetime requirements. • Developed JEDEC methodology with Quality and Reliability engineers on Flash endurance and data retention to meet customer requirements for 10,000 endurance cycling and 1 year data retention.• Qualified the first low voltage 1.8V Mirror-Bit device, with burst and simultaneous operations, for the wireless market by leading the team through multiple design spins. Product Engineer (Senior-PE1): Test program debugging, characterization, failure analysis, qualification.• Qualified and characterized first Mirror-Bit Flash, a charge trapping cell, which doubled storage from regular floating gate NOR memory. Developed screens for reliability failure modes and debugged test programs.• Resolved customer issues due to erase suspend timing which caused the device to hang by consulting with the customer. Collaborated with test engineers in replicating the issues and worked with design on a root cause fix.