As a Senior Field Application Engineer, I help bridge any gaps between what our customers need and what my company has to provide. In this role, I have written specialized and general documentation, scripts and software (Python, Tcl, Java), hardware HDL (SystemVerilog, Verilog, VHDL), and facilitate business operations. I continue to take on additional responsibilities.Part of the IP Deployment division from Magillem.

Business, IT, and software consultant at a dental practice.•Initially started with technical project: getting the office from paper office to modern digital. This involved building a server running Windows Server 2012 r2. Installed and maintained VM's with Windows Hyper-V, and the practice management software.•Trained staff on new systems and business processes. •Increased patient base through referrals, insurance coverage, marketing campaigns, and providing excellent customer service. •Evaluated and adopted Software as a service (SaaS) to streamline new patient processing, eligibility, patient communications, and billing.•Created and administered web site. Automated administrative tasks using Eclipse/PyDev/Python, Google App Scripts.

•Supported Formal Tools at Cadence with the former Jasper team in a pre and post sales role.•Orchestrated pre-sales presentations, evaluations, and wrap-up meetings closely involving R&D, sales, and executive management team members. Post-sales support for JG formal verification platform including training and scripting.•Contributed to sixty+ software change requests and created tests cases to help R&D •Successfully expanded account by exceeding customer needs and outcompeting alternate solutions

IGATE acquired Patni Computer Systems in January 2011, and Patni acquired Zaiq Technologies in May 2006.•Worked as a verification engineering consultant. Performed tools support including scripting, license management, tools evaluation, and Linux system administration.•All verification environments created from scratch using configurable self-checking random stimulus generation methodologies, and functional and code coverage written in UVM, VMM, SystemVerilog, or VHDL.•The clients and projects varied from Telecom Networking, Consumer and Enterprise Electronics, and Medical devices.

Led the random testing effort of the Southbridge ICH6 chipset. Created a testbench in VHDL and Verilog; configured random environment with XML and internal custom tools.•Developed from scratch a C++ USB 2.0 transactor modeling the low level custom voltage and NRZI encoding used in the physical layer up to higher level packets and transactions. The transactor included all components needed for proper verification such as trackers and checkers. •Implemented in advanced C++ including callbacks, multiple threads, STL vectors, and hashes.

Pre-sales and post-sales technical support of our hardware emulation/acceleration board targetedat ASIC development, and hardware/software co-verification of embedded systems.•Conducted on-site customer evaluations involving tool integration, synthesis, and place and route.•Ported demonstrations and tutorials onto various configurations and hardware platforms.•Wrote TCL and Perl scripts for tool optimization and workarounds.•Trained customers in the following areas: FPGA synthesis, transactor development based on SCE-MI standards, and ZeBu compilation and debug tools. Created test cases to reproduce bugs.•Succeeded in customer evaluations leading to $1 Million in sales in US and Canada.

Verified a highly integrated SoC device focusing on data over SONET/SDH up to OC48 rates.•Collaborated with designers and architects to improve Product Requirements Document (PRD).•Extracted information from PRD and architectural specifications to create test plans.•Estimated time and effort for verification activities. Made recommendations to improve schedule.•Created behavioral models with C++ and Verilog using Testbuilder for PLI and concurrency.•Designed a data simulation and self-checking module by encapsulating data in GFP using C++.•Responsible for all LO K4 and J2 overhead tests.•Implemented directed and full random tests.•Trained new members to the team with all aspects of our C/C++/Verilog/VHDL testbench.•Created over a dozen Perl scripts facilitating test writing and sanity checking TWB function calls.•Evaluated Specman Elite based testbench; responsible for SONET receive block.

Member of the Optical Channel Verification Intellectual Property Team. Worked on ITU-T G.709 which defines the requirements of the Optical Transport Module in terms of frame structure, functionality of overhead in the optical network, bit rates, and formats for mapping client signals. •Created a flexible, multi-case, and self-checking Forward Error Correction (FEC) test in C++ •Verified SFI-5 (Serdes interface) in the behavioral model, transactor, and the efficiency layer•Mentored junior member of the team by teaching verification methodology and test strategy•Fixed and enhanced Perl scripts for regression runs and created detailed regression results•Designed a complete overhead field test covering OH interfaces, device registers, and frame

Responsible for functional verification of a multi ASIC IO subsystem of a fault tolerant computer. •Designed and maintained random error tests and debugged corner cases in RTL and testbench.•Gained in-depth knowledge of CPU update schemes, and memory allocation solutions.•Created interrupt watchers, loggers, and checkers. Debugged and fixed RTL and BFMs.•Responsible for ASIC verification of a fault-tolerant PCI-to-PCI bridge.•Designed, documented, and implemented deterministic, pseudo-random, and high coverage random tests for simulation of fault tolerant computer systems.•Researched memory synch scheme for development of a bus functional model.•Created bus functional model for sparse memory in verification coding language “e”.•Assisted with evaluation and implementation of new tools for code coverage, formal verification, and cycle based simulation (tools include Specman, NC Verilog, Synopsis).•Verified a PCI bridge, including compliance testing for PCI 2.1 protocol.