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• Created RTL (Register Transfer Level) designs using VHDL and Verilog languages.• Developed efficient and optimized code for FPGA (Field-Programmable Gate Array) implementations.• Implemented signal processing algorithms on FPGAs.• Defined Micro architecture specifications and implementing the same using Verilog/VHDL.• Designed RTL modules specifically for FPGA and ASIC (Application-Specific Integrated Circuit) targets.• Created and developed Intellectual Property (IP) cores for reuse in designs.• Modeled and simulated algorithms using MATLAB.• Integrateed RTL components into a complete design. Perform synthesis to generate gate-level netlists.• Performed static timing analysis (STA) and clock domain crossing (CDC).• Implemented AMBA-AXI4 bus architecture on designs.• On-chip debugging of FPGA designs using Vivado hardware debug tool• Worked with high-speed data converters, including ADCs (Analog-to-Digital Converters) and DACs (Digital-to-Analog Converters).• Utilized communication protocols such as I2C, UART, SPI and USB.• Interfaced with memory components like DDR4 and FLASH.• Implemented high-speed serial interfaces like Aurora and 10GbE.• Board bring-up and validation of RTL design using TCL Script.• Functional verification of RTL Modules using Python.