S.Bharath Kumar Email & Phone Number

Have worked extensively on Static timing analysis from 16nm to 5nm chips with an experience of ~7 years. Owned timing closure for IOs - both high speed and low speed. These include PCIE, USB, MPHY - UFS, NVLINK, C2C, HDMI, DSI,CSI, SDIO, eMMC, QSPI, SPI, EQOS, I2S, I2C, DMIC etc using various PHYs and GPIO pads. Owned all clock definitions and all the constraints. Have a good understanding of whole clock and data flow on these interfaces . Also worked on timing closure at partition, chiplet (group of partitons) and top level. Some of the chiplets were multiple instantiated in a chip and also reused in series of chips which posed unique challenges. Have worked on clock distribution for these HSIOs and some chiplets - getting a good understanding on this. Other responsibilities included influencing FP , partitioning, design feedback to ease timing closure, planning at various stages of PnR to meet timing on the IO timing. Creating ECOs to fix rest of violations, applying functional ECOs on layout netlists and taking the design to TO. I am a quick learner with good grasping power who can think analytically & implement. Motivated to learn new technologies and methodologies. Ability to adapt to new situations & work effectively in group or individually. Have leadership quality and also like working as a team.

Listed skills include Ic Compiler, Prime Time, Design Compiler, Physical Design, and 37 others.