Saba Rajabi Email & Phone Number

Bay Area, United States

▪ Lead the power GaN based device design team for low-medium power device applications. ▪ Design and development of SiC and GaN power devices’ core, edge termination and ESD circuites for automotive applications.▪ Design and development of PCM devices and test instructions.▪ Cooperation with integration, test and reliability teams and foundries for new product definition and development.▪ Perform device and process TCAD simulations and device layout as part of new technology development.▪ Characterization of the electrical performances of the devices, data analysis and comparison with competitors and industry test standards (JEDEC and IEEE) and providing technical support.▪ Incorporation of design for manufacturability and determination of manufacturing tolerances.▪ Responsible for DFEMA development for GaN based devices.

Los Angeles Metropolitan Area

▪ GaN HEMT 0.15um node technology development for power efficient mmWave applications▪ Actively working with epi suppliers to engineer and enhance device performance (surface leakage, bulk leakage and on resistance)

Greater Los Angeles Area

▪ Leading GaN/AlGaN on SiC substrate HEMT for high power high frequency applications and InAlN/GaN on Si substrate MISHEMT for low voltage high frequency applications for two main customers.▪ Responsible for process integration, data analysis (DC, Pulsed, RF, Load-Pull and ESD), yield and device failure analysis through SEM, FIB, EMMI, SIMS and SPC reports. ▪ Responsible for analyzing the performed reliability tests (HTRB and ALT) and working with packaging, quality and reliability teams to meet customer requirements. ▪ Responsible for performing several fundamental studies and DOEs relating to the ESD protection implementation, Gate module and ohmic contact improvement and field plating optimization.

Davis, California

▪ Successfully designed, simulated, fabricated and characterized the first demonstration of “N-polar GaN based CAVET transistor for high frequency high power Switching” under the DARPA (Defense Advanced Research Projects Agency) YFA program.▪ Developed the full III-V compound semiconductor device process in a 100-class cleanroom; trained on tools and developed recipes for Photolithography techniques (i-line stepper); Thin film deposition (PECVD, E-Beam Evaporation, DC and RF reactive Sputtering and ALD); Chemical and plasma etching (wet etch, RIE, ICP); Metrology tools including surface profilometry, Optical Profilometer, and Ellipsometer; Microscopy and analytical techniques including AFM, SEM, EDX, Hall Measurement, I-V, Pulsed I-V, C-V analysis, TLM measurement, high temperature and high voltage analysis of power semiconductor devices; Micro-probing including DC and Pulsed characterization using semiconductor parameter analyzer and curve tracer.▪ Developed a TCAD simulation (process/device/circuit integration) platform for power devices using Silvaco: I helped Silvaco TCAD team to develop the standard simulation models for GaN MOSFETs.▪ Developed a Mg ion implanted GaN layer behaving as P-GaN current blocking layer.

Tempe, Arizona

▪ Responsible for TCAD simulation and modeling the static behavior of programmable metallization non-volatile memory cells and calibrated it to the measured data, under the AFRL and DTRA program.

Doctor Of Philosophy - Phd, Electrical And Electronics Engineering

Phd Candidate, Electrical And Electronics Engineering

Master Of Science - Ms, Electrical And Electronics Engineering