Sadeka A. Email and Phone Number

Work Experience: High Speed IO and precision analog circuits such as, CTLE for high speed Receiver AFE, PCIE Gen3 Transmitter Driver, Continuous time Filter, Compensation blocks, PLL, DAC,LDO, TPM in deep sub-micron Finfet technologies. Specialized in specification development and leading circuit and post silicon measurement teams. Interacted with cross geo teams and delivered multiple products and test chips with proven silicon. Responsibilities include:*Continuous time Filter design for AFE, Phase Interpolator design in 7nm and 12nm FF technology*24GHz LC PLL design with low phase noise for Serdes Phy in 12 nm FF*25GBps Linear equalizer [CTLE] based Receiver AFE design and feasibility research in 14nm CMOS*Current steering DAC for Linear Equalizer in 22nm CMOS technology*25GBps TX driver and front end design feasibility research*Designed TX driver for PCIE Gen3 test chip @ 8Gb/s with proven silicon.*Designed Global compensation [GRC] for receiver and transmitter. *Designed on-die linear regulators(LDO) with proven silicon*Designed Transmit Power Monitor [TPM], DAC in 10G Transceiver with silicon