🚀 Sankalp Dev | VLSI Design EngineerAs a seasoned VLSI enthusiast with an M.Tech in VLSI Design and professional experience at MathWorks and Calligo Technologies, I specialize in IP block design, FPGA development,dynamic function exchange,verification and RTL design.🛠️ Key Projects:Leveraged Xilinx's DFX to enhance FPGA reconfiguration efficiency.Implemented FPGA-in-Loop Hardware Test Support using MATLAB HDL Coder.Executed Verilog HDL projects at Calligo, showcasing expertise in AMBA AXI protocols.💡 Skills:Hardware: Verilog, System Verilog, UVM, Digital Design.Digital Concepts: IP Block Design, FPGA, Static Timing Analysis.Simulation Tools: MATLAB, Sentaurus TCAD, NgSpice.Programming: Python, C, C++, OOP in C++.🌐 Passionate about advancing VLSI technology and contributing to innovative projects. Let's connect and explore opportunities in the dynamic world of VLSI design!