GlobalFoundries Pvt. Ltd., Singapore Process Integration Engineer 0.18um Silicon Photonics, Lightwire and IC Process Jan’14 to present• New product development for Silicon Photonics. Worked together with our developing partner for process development and also to understand product requirement/issues and provide the best solutions.• Worked with Unit Module development team to run DoE, Construction Analysis and margin split to find the process weakness and to make the process more robust and increase device performance • Spearhead the planning and development of inter-fab transfer Lighwire process• Successfully improved transistor performance in PMIC devices in order to meet rigorous speed requirementOxide Field Trench Power and Split Gate MOSFET Development Jul’13 to Mar’14 • Spearhead the planning and implementation of process transfer of OFT1 project from mother fab to GF• Improved baseline yield through DOE, failure analysis, and teamwork with process engineering• Investigated excursion events, discovered root cause, and provided containment/permanent solution• Qualified the product for risk production of Split Gate and improve yield by improving Inline D0• Performed monitoring and investigation of Inline and ET Statistical Process Control (SPC) charts• Maximize fab output and reduce cost through process qualification and process changes.ALPHA Training Aug’12 to Jul’13• Exceled in all advance technology node process (Mature technologies power MOSFET to 40nm Bulk/SOI)• Familiarized with over all Process flow, Device physics, Stress Engineering, module aspects

• Developed the complete SoC verification environment using System Verilog to functionally verify LTE FPGA using Modelsim. This involved architecting verification plan and coding the test cases accordingly• Actively involved in developing verification environment for DUT using Verilog and System Verilog (whichinvolves development of constraint random verification, Assertions, Checkers, Scoreboards, Monitors,Functional coverage, code coverage, Directed tests and Random tests development)• Spearheaded a team of 4 members and mentored with developing testbench and reviewing test plans.• Established the Verification environment for migration of AHB to AXI and FPGA to ASIC• Validated the peripheral such as RFIC, DigRF, MPHY and MDDR as per the specifications and worked withvendors to verify thoroughly and also involved in integration of the peripherals to the DUT and performedoverall testing.• Spearheaded Perforce and bug tracking systems implementations and debugged all the RTL bugs till root causelevel and worked with design engineers to fix the bug• Developed traffic generator in a traffic profile to verify AXI protocol transactions• Developed automation scripts using Bash and Perl to test regressively and enabling coverage• Involved in debugging and testing Hardware board using JTAG cable, Oscilloscope and Logic Analyzer• Developed the Application Programmable interface tool kit using Perl and C#.Net to communicate with theBase station and run over night regression and presented the demo to the client on the same