Sagnik Barat Email & Phone Number

Project Engineer (Synthesis)VLSI Domain Skills: >> Domain: Synthesis (logical and physical aware). >> Tools: Fusion compiler, Genus, Innovus >> Core Skills: Timing and congestion analysis, STA, LEC, CLP >> Scripting Language: TCL, perl >> Good in Linux EnvironmentSubject Expertise: >> Digital and Analog Electronics. >> Digital IC Design. >> CMOS Fundamentals. >> DFT fundamentals Soft Skills: >> Team Work >> Good at Conflict Resolution >> Passionate and Focused

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  Project Engineer

  Synapse Techno Design Innovations Private Limited

  Jun 2022 - Present - Bengaluru, Karnataka, India

  Project 3Description: physical aware synthesis with timing and congestion analysis and fix. QC checks like LEC, ERC, CCF. DFT insertion and ATPG.client: Mediatek chip type:- displayTechnology node: 3 nmTools: Fusion Compiler, Formality Project: 2Description: physical aware synthesis with timing and congestion analysis and fix. QC checks like LEC, ERC, CCF. DFT insertion and ATPG.client: Mediatek chip type:- displayTechnology node: 12 nmTools: Genus, Innovus Ispatial, Cadence ConformalProject: 1Description:- Physical aware synthesis and Floorplan def generation.Technology node: 5 nmClient: AMDChip Type: GraphicsTools: Fusion Compiler