Extensive experience in Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, and conducting Lint, synthesis, CDC, FV, and LEC checks. Proficient in developing RTL implementations that consistently meet competitive power, performance, and area targets. Highly skilled in synthesis, timing and power closure, and FPGA/silicon bring-up processes.Always eager to take on technical challenges and solve them with determination. I enjoy working in a team and am fully committed to achieving our shared goals.