Saikat Mukherjee Email & Phone Number

Bengaluru, Ka, In

Bengaluru, Karnataka, India

* Managing CPU sub systems across multiple CPU cores * Methodology / Tech Readiness Lead in deep sub-micron technology.

* Leading physical design convergence at sub system level from tech readiness to integration for a cpu cluster * Quality / Signoff methodology development across process nodes* Mentor Junior DEs for technical career path

Bengaluru, Karnataka, India

Responsible for End-to-End quality check In IP design & signoff domain to customers both internal & external, Role also includes certifying signoff flows like formal verification, low power checks, layout checks & timing closure checks.Regular contribution to Physical Design Methodology improvements by flow & quality check scripts.

Bangalore

* RTL to GDS implementation (synthesis, placement, cts, timing analysis) of 2 physical partition of Intel 65nm chipset & FC noise owner of Intel 65nm chipset * synthesis, placement, cts, timing analysis of large partition of Intel 32nm chipset with multiple clock domains.* RTL to GDS implementation of Intel CPU blocks in below 32nm technology & multi giga hertz frequency* Section Power Leadership & low power optimization methodology development in deep sub-micron domain.* Low Power Synthesis & clocktree flow developments using synopsis power compiler

Bangalore

# RTL to GDS implementation of large Physical partitions for Intel Chipset# Full Chip Noise Flow Owner Ownership for Intel Chipset

Bangalore

* Synthesis,Placement, CTS & timing analysis of 2d graphics hard macro * Boundary scan, physical synthesis & timing analysis of ARM7 based microcontroller in 130nm technology* Top Down physical design planning & execution (synthesis, placement, cts & timing analysis) of large Display chip(~ 1million gates) in 180nm technology

* design & verification of multiple IPs in set top box SOC* Synthesis(DC), Placement (physical comp) , Static Timing Analysis (PT) & DFT analysis(tetra max) of 2 large physical blocks (> 300k instances) for Set top box SOC in 180nm technology.

* Design & verfication of MPEG4 Decoder ,Synthesis & timing analysis* Design, Verification & Physical implementation of Motion Estimation block (halfpel algorithm) in MPEG4 encoder.

Digital Product Decarbonisation, Carbon Management

Ms Microelectronics, Microelectronics, First Class With Distinction

B.E, Instrumentation & Electronics

Activities and Societies: Technical Quiz & presentations