Saikat Mukherjee

Saikat Mukherjee Email and Phone Number

Sr Manager Gfx Engineering @ AMD
Bengaluru, KA, IN
Saikat Mukherjee's Location
Bengaluru, Karnataka, India, India
About Saikat Mukherjee

Saikat has 23 yrs experience in physical design in graphics , cpu design and mixed signal domains. He has strong background in managing teams towards high quality convergence at section , full chip & IP level. He is well versed with industry standard tools like Fusion Compiler,DC, ICC , prime time & Cadence genus,innovus. Saikat has specialisation in Low Power design convergence using industry standard tools like spyglass, VCLP and PrimePower.Saikat leads methodology development across timing, low power and reliability domains & including improvisation using AI / ML solutions.Saikat specialises in data visualisation & analysis using industry standard tools like splunk.

Saikat Mukherjee's Current Company Details
AMD

Amd

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Sr Manager Gfx Engineering
Bengaluru, KA, IN
Website:
amd.com
Employees:
44382
Saikat Mukherjee Work Experience Details
  • Amd
    Sr Manager Gfx Engineering
    Amd
    Bengaluru, Ka, In
  • Amd
    Sr Manager Silicon Design Engineering
    Amd Jun 2022 - Present
    Bengaluru, Karnataka, India
    * Managing CPU sub systems across multiple CPU cores * Methodology / Tech Readiness Lead in deep sub-micron technology.
  • Intel Corporation
    Senior Tech Lead Cpu Core & Client Development Group
    Intel Corporation Oct 2020 - Jul 2022
    * Leading physical design convergence at sub system level from tech readiness to integration for a cpu cluster * Quality / Signoff methodology development across process nodes* Mentor Junior DEs for technical career path
  • Intel Corporation
    Sd Manager & Signoff Lead Ipg
    Intel Corporation Jul 2014 - Sep 2020
    Bengaluru, Karnataka, India
    Responsible for End-to-End quality check In IP design & signoff domain to customers both internal & external, Role also includes certifying signoff flows like formal verification, low power checks, layout checks & timing closure checks.Regular contribution to Physical Design Methodology improvements by flow & quality check scripts.
  • Intel Corporation
    Low Power Lead In Intel Cpu Design Team
    Intel Corporation Mar 2010 - Jul 2014
    Bangalore
    * RTL to GDS implementation (synthesis, placement, cts, timing analysis) of 2 physical partition of Intel 65nm chipset & FC noise owner of Intel 65nm chipset * synthesis, placement, cts, timing analysis of large partition of Intel 32nm chipset with multiple clock domains.* RTL to GDS implementation of Intel CPU blocks in below 32nm technology & multi giga hertz frequency* Section Power Leadership & low power optimization methodology development in deep sub-micron domain.* Low Power Synthesis & clocktree flow developments using synopsis power compiler
  • Intel Corporation
    Senior Design Engineer Intel Axg Group
    Intel Corporation Nov 2005 - Mar 2010
    Bangalore
    # RTL to GDS implementation of large Physical partitions for Intel Chipset# Full Chip Noise Flow Owner Ownership for Intel Chipset
  • National Semiconductor
    Design Engineer
    National Semiconductor Feb 2004 - Nov 2005
    Bangalore
    * Synthesis,Placement, CTS & timing analysis of 2d graphics hard macro * Boundary scan, physical synthesis & timing analysis of ARM7 based microcontroller in 130nm technology* Top Down physical design planning & execution (synthesis, placement, cts & timing analysis) of large Display chip(~ 1million gates) in 180nm technology
  • St Microelectronics
    Associate Design Engineer
    St Microelectronics Mar 2003 - Feb 2004
    * design & verification of multiple IPs in set top box SOC* Synthesis(DC), Placement (physical comp) , Static Timing Analysis (PT) & DFT analysis(tetra max) of 2 large physical blocks (> 300k instances) for Set top box SOC in 180nm technology.
  • U&I Systems Design
    Member Technical Asic
    U&I Systems Design Sep 2000 - Mar 2002
    * Design & verfication of MPEG4 Decoder ,Synthesis & timing analysis* Design, Verification & Physical implementation of Motion Estimation block (halfpel algorithm) in MPEG4 encoder.

Saikat Mukherjee Education Details

Frequently Asked Questions about Saikat Mukherjee

What company does Saikat Mukherjee work for?

Saikat Mukherjee works for Amd

What is Saikat Mukherjee's role at the current company?

Saikat Mukherjee's current role is Sr Manager Gfx Engineering.

What schools did Saikat Mukherjee attend?

Saikat Mukherjee attended Terra.do, Manipal University, Bangalore University.

Who are Saikat Mukherjee's colleagues?

Saikat Mukherjee's colleagues are Ling Yang, Harry Sharma, Soko Gloria .o., Mojtaba Alizadehledari, Weipeng (Sga) Sun, Neha Shrivastava, Kathyayini Yr.

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