Design verification of WiFi PHY layer protocols.1) Proficient in IEEE 802.11 a/n/ac/ax/beWiFi standards2) Expertise in System Verilog and UVM based testbench environments3) Functional verification of PHY - Radio interface4) Log parsing python based Automation.

Worked on transactor development and peripherals validation for next gen Prototyping PlatformProtocols: JTAG, AMBA, AXI, 1)VJTAG Transactor development:Developed VJTAG for Prototyping platform which can eliminate physical JTAG. Debugged complex hardware / software issues quickly to enable early deployment at customer.2) LP5 and LP4 memory model development. 3) Worked on integration of transactors with debuggers like lauterbach Trace 32 for enabling SOC debug and early software bring up on emulation4) All Peripherals in SOC validation with new hardware and co emu platform.

Post silicon Debug validation Engineer, Experience in Mobile chips and the modem chips.Roles and Responsibilities:1) Enabling Debug tool with various feature support for the Engineers to debug2) Applying Hardware traces, Identifying Hardware bugs in the Debug Architecture4) Collaborating with design team to add new features in Debug Architecture to ease the Jebug5) Enabling and Handling arm CoreSightArchitecture for debug in multiple projects6) ReArchitecting the existing tool including package manager, Distribution, Installation to Enhance the feature set, user scalability and hardware traces like ETM, STM and other ATB traces.

RTL Design and verification in aerospace Domain.1) Designed FPGA based Verification environment from scratch. 2) FPGA Requirements writing and analysis by reverse engineering existing Hardware. 3) D0-254.4) functional verification and simulation.