Sajeed Mohammad Email & Phone Number

San Jose, California, United States

San Jose, California, United States

• Developed a comprehensive evaluation plan and criteria to assess the Imperas tool and verified the RISC-V processor using the tool.• Conducted verification of RISC-V processor and IPs using formal properties and methodologies.• Engineered a verification framework utilizing formal methods to validate cryptographic accelerator IPs and quantum-safe engine IPs RTL designs.

Gainesville, Florida Area

• Researcher in Hardware security, verification, design, firmware security, and secure boot process.

Hillsboro, Oregon, United States

• Designed a library of core RTL components to be integrated into fast-paced SoC development.• Developed a formal and simulation-based verification framework to verify pre-silicon designs.

• Research Program: GRC Hardware Security "Extensible Secure SoC Architectures"• Research Description: A standards-based security engine (SE) architecture and platform incorporating innovative countermeasures that respond to extensible threat methodology and demonstrating the integration of countermeasures that improve baseline vulnerability metrics on an example implementation.• Research Area: Formal Verification, Hardware Security and Trust, CAD Tools, Secure SoC Development, Supply Chain Attacks and Security

Hyderabad, Telangana, India

Doctor Of Philosophy - Phd, Electrical And Computer Engineering, 3.7/4

Activities and Societies: Indian Graduate Student Association (IGSA)My research is focused on developing a secure and configurable SoC..

Graduate Certificate, Hardware And Systems Security

The Hardware and Systems Security (HSS) graduate certificate is a distinctive offering that provides comprehensive training and education.

Master'S Degree, Electrical And Computer Engineering, 3.66/4

Activities and Societies: Indian Graduate Student Association (IGSA)

Bachelor Of Technology, Electrical, Electronics And Communications Engineering, 8.26/10