Sam Boon Email & Phone Number

* Architecture design and template coding of Host to Front End and Back End validation and firmwarecode through Circular Buffer data structures and algorithm and RISC-V interrupts.• IPC code design between Control processor CCP and PE and vice versa..• RISC-V interrupt mechanism coding.• PLIC interrupt coding..• Design and Interaction of PE monitor with Glow code through function pointers.• 128 core single boot code image development..• Coding in C and RISC-V assembly.• Managed a team of 2 validation engineers and 4 firmware engineers.

San Bruno, California, Us

• ARM Cortex M0 and M3 Bootloader development.• SPI Device Driver debug on Linux OS.• OTA Firmware Download Module development.• Debugged software race condition issue during SPI packet transfers between a CPU running Linuxand a MCU running Bare Metal code.• BLE firmware development on bare metal.• Firmware development on ARM Cortex M0 and ARM Cortex M3.• LED driver development for concurrent LED pattern display.• Removed delay function from LED display operation using interrupts and scheduler.• Firmware development with Sensors, Watchdog Timer and Counter.• Low power embedded firmware design and development.• Interrupt based UART firmware development.• BLE stack layer 2 tuning for BLE advertisement interval and connection interval.* Coding in C.* Managed a team of 3 engineers.

Santa Clara, California, Us

 NVME PCIE Client SSD software bug issue resolution and root cause analysis. Issues included PCIE link down,command timeout, SSD will not boot upon unplanned shutdown event from host. The issues will be resolved byinterpolating UART logs, log events inside NAND & DRAM and PCIE bus analyzer capture traces. CPU complexconsisted of ARM dual core integrated with L1 Cache, ITCM, DTCM and STCM. Peek Poke Vendor Unique Command tests like read, write & erase on B0KB and B16 INTEL NAND. Modification & patches to Mark Bad Block and Garbage Collection module. Good understanding of pretestmanufacturing flow, FTL, Garbage Collection, Trim, SLC and TLC NAND read/write/erase process, SRAM, DDR &PCIE. Write and Read SSD data flow end to end Answered questions of Intel Engineers directed at all of NVME PCIE SSD. Documentation on Pretest, Peek Poke,DST, Mark Bad, Wear Levelling, Trim and Garbage Collection process. NVME host test scripts using Python. AES 256 initialization & key storage code and TCG OPAL security module testing. MBIST testing with DRAM. NAND mode change testing from SLC to TLC and vice versa. NVME controller testing with JTAG SCAN. API library for 20 System Timer & 80 CPU Timer for SSD. The timers will generate event and interrupt uponexpiration. Firmware to manage system critical data in SPI NOR flash and API library to maintain data for several front endand back end modules. IPC module development. Linker script to put the Firmware data in a different section of physical SRAM. This data included state of SSDboot, state of SSD firmware and SSD firmware image download. PCIe 3.0 SERDES configuration parameters configuration & optimization. Good understanding of UEFI. Coding in C and C++. Managed a team of 4 engineers.

San Jose, Ca, Us

 Linux Kernel SYS FS software command for Automatic Voltage Scaling chip. CPU consisted of 8 core ARM. Thesystem was CAT 4K ethernet switch and router. Linux Kernel panic issue resolution on switch boot up when USB host and USB device on same board wereloopback. Verified working of ROM monitor application from UBOOT. Built periodic Linux and UBOOT images for the team. PCIE scan test for 100 Giga bps port Switch for new components. Diagnostic tests for testing the features of BIOS and UEFI in 100 Giga bps port Switch. Utilities for extracting, erasing, programming and verifying BIOS firmware components. Voltage margining andtemperature sensors diagnostics code debug with JTAG SCAN and IDE. MBIST testing on memory modules. Tested VLAN, switching and routing functionality of 100 Giga bps port switch and router. Functional & manufacturing validation tests in Python and C++. Test vectors generation using ATPG. Tests for Clock Monitor, PLL, Voltage monitor, I2C, MDIO, Temperature Sensor and Optical Modules. Data path traffic validation tests on QNX OS with external 100 gigabit Ethernet traffic tester. Broadcom gearbox PHY ASIC module PRBS and loopback diagnostic tests. 100 Giga bps line card interrupt tests. Validation and functional bring up of 100 Giga bps line card with ARM based CPU complex on QNX OS. PCIe 3.0 and 100Gbps Ethernet SERDES bring up and waveform data capture at TX and RX points. Thermal management tests. Power measurements tests. Test software automation. Tested DDR, I2C and SPI buses for signal integrity and protocol measurements. Coding in C and C++.

Palo Alto, California, Us

 Fixed bugs in USB 2.0 and SD 3.0 drivers that came from external customers. Added DMA functionality to UART driver on THREADX RTOS. Enhanced SD 2.0 driver to SD 3.0 driver on THREADX RTOS. Performance testing on SOC AXI bus, masters and slaves transmitting and receiving concurrently. This was doneon embedded LINUX in multithreading mode to test the leakage issues in arbitration logic of AXI bus. UBOOT NAND driver issue resolution related to NAND controller ECC hardware race condition. Developed UBOOT “GO” command applications to manipulate addresses of the application for the sake ofUBOOT remote firmware upgrade. Debugged Linux Ethernet TCP/IP Applications for packet drop and Socket System call hang. Wrong usage ofmutex was the cause of hang. MBIST, OTP hardware validation on FPGA using JTAG. OTP module firmware development on THREADX. USB, PCIE & SDIO host interface validation on FPGA. Post silicon validation of Broadcom multiple ARM basedSOC internal busses. USB SERDES configuration tuning. Coding in C and C++.

San Diego, Ca, Us

 Validation driver firmware for USB 2.0 host controller & USB 2.0 device controller core on bare metal. Led a team of 3 engineers to validate Smart Peripheral System. SPS is direct USB to SD/SDIO data transferwithout central CPU & system memory involved. SPS increase data transfer throughput by 60 percent. Pre & post silicon validation TSIF, High Speed UART, I2C, SPI, SD, MMC, SDIO, CE-ATA, PCIE, SATA, RegisterProtection Unit, Address Protection Unit, Memory Protection Unit, Touch Screen Controller & CryptographyEngine. AXI and SD bus latency measurements to root cause the low throughput of SD bus as reported by customer HTC. C code optimization on ARM & arbitration logic correction applied on SOC. Thermal tests and Power measurement tests. SOC debug using JTAG and Boundary Scan. Design of SOC MBIST. Coding in C.

Geneva, Switzerland, Ch

 Efficient IRQ & FIQ Interrupt Handler software in ARM assembly using binary search and look up tables. Field Application Reject analysis of SOC based on two DSP and 8051 coming from BOSE. The symptom of theissues were noise coming out of one channel or more audio channels or no output from a specific channel. Theroot cause were mostly due to memory corruption. Display tool using ARM7, SPI, UART and PC hyper-terminal program. Test plan design and validation of Bluetooth core and High Speed UART core. Validated SOC low power modes and domains by slowing clocks, shutting clocks and shutting off power domains. Validated BT operation between multiple BT devices. NOR flash hardware drivers. Validation of ST SOC internal peripherals Capture Compare and I2S. Test pattern generation through ATPG for testing BOSE audio amplifiers and ATE. Coding in C. Managed a team of 3 engineers.

 The product was a single board pizza box gigabit ethernet policy enforcer containing 3 MIPS and 9 NetworkProcessors. Each MIPS controlled 3 Network Processors. Multi MIPS boot up and auto detect SDRAMinitialization boot code. Ported Nucleus PLUS RTOS to IDT MIPS hardware. Real Time Clock using 10ms timer interrupt and MIPS interrupts. Multi MIPS software semaphore for serial RTChardware access. Inter MIPS communication module using shared memory & MIPS interrupts. PCI, FLASH, LCD, LED, I2C, UART, NVRAM & RTC low level drivers. Gigabit Ethernet Device Driver on Nucleus PLUS TCP/IP stack. Firmware download module over UDP. Coding in assembly language for VITESSEE Network Processing Unit. Coding in C. Managed a team of 6 engineers.

 MOTOROLLA 32 bit processor based Passive Optical Network and SONET system software development. OHP board Exchange Call Originating & Terminating process software for SONET. SONET Configuration & Fault Management GUI software using Visual C++ and UART Windows Driver. CTS board Configuration, Fault & Event Management Processes on RTOS. Board schematics development. Coding in C and C++. Managed a team of 12 engineers.

Master Of Technology - Mtech, Computer Engineering

Bachelor Of Engineering - Be, Electronics And Communications Engineering

High School Diploma, Maths Physics Chemistry English