Lead a team on system centric pathfinding of Si, package and board integration technology to enhance chipset performance and reliability for HPC and mobile applications: • Sub 7nm node system pathfinding: Investigating the PPA scaling trend/limits for logic, RAM and analog circuits, and memory walls with device and circuit teams; pathfinding more than Moore solutions with foundry to address chipset performance/cost gap; generated advanced interconnect (MCM, Si interopser, Fanout, 3D) roadmap for mobile and HPC chipsets to meet design targets. • Memory to Logic 3D integration: Working with chip architects, defined/optimized memory+logic 3DSiC stacks architecture to provide ~10X memory BW and ~10X D2D IO power reduction for HPC chips, qualifying the technology at foundry with test structures to address process, reliability, CPI and thermal mechanical risks. • Chip-package-board interaction (SI/PI, thermal/ mechanical): Developed a comprehensive methodology to quantify thermal and mechanical limits of the fan-out mobile AP chip on board, and generated design rules for analog designers, and co-optimized the FANOUT and Si stack to improve chipset PDN by ~15mV for Vddmin and reduce noise coupling by 3 dB without process cost adders.

Managed a team of experts on Si device, process, assembly and laminate substrate to pathfind/enable disruptive technologies to provide competitive product advantages. Key accomplishments: • Si process pathfinding: Interface with IBM alliance on 45 LP node, benchmarked process capability from multiple foundries and IDM, refined the design rules from foundry for 45 and 32-28 nm node for optimal PPAC. Managed IMEC technical interface for earlier look of sub 16nm node on FEOL, BEOL, litho, logic insites and 3D,• Memory IP pathfinding: Benchmarked the nonvolatile RAM IPs for retention, endurance, power, area and process adders. Qualified OTP into PMIC chips, which reduced output voltage variation by ~10X. Benchmarked and refined eDRAM from multiple foundries, enabled eDRAM IP into CSM products. Defined and developed wide IO memory with Samsung.• Memory to SOC 3D TSV integration: Defined and developed 3D TSV stacking integration (via middle 5/50 um Ø/H, 40 um pitch ubump). Successfully demonstrated industry first WIO cube stacking on the backside of 28 nm SOC with TSV. • Chip-package integration: Characterize the BEOL/package scaling limits, and process/design impact to device/circuit performance and reliability. • RF: Explored integration options of passives, filters, switches and PA for optimal performance and small form factor for RF-FE modules. • System in package (SIP) for split die reintegration: Successfully demonstrated low cost Si interposer, fine pitch RDL on laminate substrate, and fine pitch fan out at wafer (INFO, eWLB) and panel level (eWLB), and combination low cost Si and fanout with POP memory stack capability.

Led a process integration team on a CMOS line to develop process for storage products. Key accomplishment: • Developed a process flow to integrate carbon nanotubes (CNTs) into non-volatile memory (NVM) devices and fabricated the 1st working CNT NVM switches on 8 inch wafers. • Developed Cu/low K BEOL process modules for 90/65nm node. Optimized the BEOL processes to minimize damage to porous low K (K values of 2.5 and 2.2) and Cu, and developed local interconnect modules to improve routing efficiency, FEOL processes for high K gate dialectics integration and transistor drive current improvement.• Developed 130nm (C13) Cu/FSG foundry compatible process and coordinated the module activities for 15 engineers, demonstrated yield for SRAM and Logic devices.

As a member of fab start up, I had owned etch/clean module during start up, led yield enhancement, and the 0.18 um (C18) foundry compatible BEOL integration. Key accomplishments:• Developed 0.18um Al/FSG MOL and BEOL flow which included borderless contact /via modules.• Transferred LSI 0.18 um (G12) node technology from Santa Clara R&D fab into Gresham production fab, and from Gresham to Silterra foundry in Malaysia. Led the plug module team for the process qualification and yield improvement in Gresham. Implemented design density verification process, which eliminated the catastrophic yield loss due to the poor pattern density issues.• Closed 7 major defect cases including gate oxide integrity, poor silicide formation and high via resistance problem, which significantly improved line yield, sort yield and device reliability

Carried out research on IIIV opti-electronics (quantum wires and quantum dots) and integrated optics (optical amplifier). Fabricate the first GaN blue LEDs at the university.