Sam Tower Email & Phone Number

Cupertino, California, Us

Optimizing timing, area, power, and power delivery by using cutting edge software to create custom flows. Managing signoff limits to balance margins, execution speed, and design quality. Use production data and creating custom silicon on newest tech nodes to verify implementation quality of flows and limits. Always looking for world class talent to ensure Apple stays an industry leader.

Lead a team of 5 responsible for working with P&R, timing, technology, clock, and custom circuit teams to implement optimal power gird and IVD fixing strategyAdvised teams across Samsung on IVD timing, how to resolve system power delivery problems, and on die IVD issuesManaged technical relationship with IR/IVD tool vendorHelped move the industry forward on IVD impact on timing by working with many vendors and making presentations at conferencesSet goals and reviewed all clocks/power grid/IR results prior to tapeoutHelped define next generation process technology by providing data predicting our future needsNegotiated updates to current generation process technology based on implementation needsWorked with lab, custom circuit, architecture teams to develop and implement techniques to control voltage drop to reduce powerHelped debug silicon issuesCo-developed flow for running and verifying results of IR/IVD tool (Coded in Ruby)Generated hundreds of scripts to extract information, convert file formats, monitor systems, setup simulations, speed update simulations, and more

Responsible for reducing power and skew on custom clocks for multiple high performance CPU designs.Taught new team at SARC and teams in Korea how to build high performance custom clocksCo-developed custom clock implementation tool. It places cells and creates balanced routes with a simple user interface (Coded in Ruby & C++)

Developed custom circuits to enable high performance ARM CPU team.Developed custom scripts to speed up critical pathsMade key contributions to tapeout of the first chip at the Austin design center. This included working on custom circuit blocks, digital blocks, and CAD flowsDeveloped and reviewed cells in digital library to improve speed, size, power, and reliabilityRecommended / implemented many changes to characterization and margining of standard cell flow

Austin, Texas, Us

In the cellular products division working most of the time with the ARM core team I would develop custom circuits, research and integrate innovative power saving techniques, and analyze next generation technologies and CAD tools. - Evaluation of next generation technology (C40) which includes review of vendors offerings. Reverse engineer cells to test robustness and make a fair comparison between vendors. Evaluation done with spice and STA.- Review of schematics and layout of cells in digital library to improve speed, size, power, and reliability. - Developed and released pulse flop to ARM team that will speed up the design by 10%. Used Monte-Carlo sims to margin pulse width. Patent has been filed.- Worked to validate and improve Cadence’s SSTA(statistical static timing analysis) tool. Used Si results to verify both spice and interconnect models while testing the SSTA flow. - Analyzed technology to predict optimum minimum DVFS operating voltage for current technology and chip. Managed and implemented the required updates to the libraries to enable the target.- Helped develop a power saving technique that reduces the average power of a distribution of parts.- Created testchips in C65 to verify functionality of SRPG flops and test for different types of process variables. Used results to assess risks in the design flow and how to improve cells we build.- Supervised the technical aspects of a portion of a C45 test vehicle.

San Jose, Ca, Us

(2004-2005) Technology ImplementationSupport and develop physical verification decks, add new devices to schematic and layout flows, verify models work with tools in the cadflow. Brought in to streamline and catch up the group.- Redefined Technology Implementation Process Spec and created training reference website. - Developed and supported innovative technologies for Assura and Calibre. For instance MRAM.- Created ruby script that automatically verifies models in 3 simulators- Implemented ruby script to verify the tapeout paperwork in the flow matches the spec(2002-2004) Cypress Verilog-A Expert and Responsible for Analog Side of the Mixed Signal Flow- Creation of training materials- Teaching entire company around the world how to use the tools- Development assistance for Verilog-A mixed signal models from PLL's to standard cells- Provided internal CAD flow support - Worked with vendors to prioritize and resolve issues(2001-2002) DESIGN Engineer - Noise Simulations for USB chip- Design Liaison to CAD