Sameer Shaikh

Sameer Shaikh Email and Phone Number

General Manager (Head of Hardware Engineering, 5G Business) @ HFCL Limited
new delhi, nct, india
Sameer Shaikh's Location
Bengaluru, Karnataka, India, India
About Sameer Shaikh

A Hardware Design Engineering professional with over 2 decades of hands-on experience primarily in High-Speed Digital Board Design and knowledge of RF design concepts in Telecom, Networking and Quantum Domains. Worked in multiple product-based startups and MNCs involved in the design of cutting-edge technologies.• Performance-driven professional with over 20 years of rich and extensive experience in the complete product life cycle of Hardware System Design from proposal of architecture, freezing requirements, Component selection, Architecture design, Schematic capture, Signal Integrity, Power Integrity, PCB Design, Board bring-up, System Testing/Debug, Mechanical and Thermal design and product Qualification.• Hands-on experience in designing the different types of complex high-speed Digital boards.• Responsible for ensuring High Quality Hardware Design of multiple 5G Wireless based Radio Units (RU/RH) for both Indoor and Outdoor Environments as per O-RAN standards.• Responsible for ensuring complete RF Analog and Digital Hardware Design of Single Photon Detector (SPD) System with the target of achieving 50% photon detection efficiency at 10ns detection dead time with Gating Frequency of 1GHz to be used in a Quantum Technology based QKD product.• While in Broadcom, skilled in designing multiple PCB Boards (max 24 layers) for validating and Characterizing Broadcom's XLR, XLS, XLP and Vulcan series of Multicore, Multithreaded Processor SoC family designed to address IP networking, VoIP, wireless LAN, 3G wireless, broadband, storage, routing and switching, security and telecommunication applications.• Experience in designing multi–Digital Signal Processors based products (using array of 20 DSP chipsets) for voice and data compression right from concept to successful field trials and final deployment. • Sound knowledge in the design of boards with FPGAs such as ALTERA’s Stratix-II and XILINX’s Spartan-II, Virtex-5 series and Zync Ultrascale (+RFSoC). Also used CPLDs such as those from Altera and Lattice (MachXO). • Designed boards using SoC processors such as NXP’s LX1046, NXP’s LS1234, Broadcom’s XLR/XLP/XLS series, Netlogic’s Knowledge Based Processor (KBP) and FREESCALE processors such as DSP563xx, MPC8247, MPC8260, MSC8144 and MPC8360.• Experience in Hardware design of interfaces such as DDR2/3/4, PCIE Gen 3/4, MII/RGMII/SGMII/XFI/XGMII, XAUI/XLAUI, Serial RapidIO, SATA, ICI, HyperTransport, Serial RocketIO, USB 2.0/3.0, SFP/SFP+/SFP25/QSP/QSP25, NOR/NAND Flash, SDHC/eMMC, RS232, RS485, SPI, I2C, TDM E1, SONET/SDH STM-1/4/16.

Sameer Shaikh's Current Company Details
HFCL Limited

Hfcl Limited

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General Manager (Head of Hardware Engineering, 5G Business)
new delhi, nct, india
Website:
hfcl.com
Employees:
956
Sameer Shaikh Work Experience Details
  • Hfcl Limited
    General Manager (Head Of Hardware Engineering, 5G Wireless)
    Hfcl Limited Sep 2021 - Present
    Bengaluru, Karnataka, India
    • Presently working on final stages of 5G Macro RU 8T8R and 5G All in One Small Cell 2T2R products• Responsible for ensuring delivery of a high quality and low-cost prototype builds through all the stages of development: functional specification, HRS, HDD, component identification, schematic design, PCB layout, mechanical/thermal design, PCB assembly, board bring-up, DVT, system testing, pre-compliance and compliance testing.• Each system is designed using multiple boards for… Show more • Presently working on final stages of 5G Macro RU 8T8R and 5G All in One Small Cell 2T2R products• Responsible for ensuring delivery of a high quality and low-cost prototype builds through all the stages of development: functional specification, HRS, HDD, component identification, schematic design, PCB layout, mechanical/thermal design, PCB assembly, board bring-up, DVT, system testing, pre-compliance and compliance testing.• Each system is designed using multiple boards for scalability and for meeting the mechanical, thermal and isolation requirements.• Use of multiple processors/devices for handling of L2-L3 switching, L1 and PHY functionalities. • Option for synchronizing the timing of entire system using either PTP, SyncE, GPS or holdover modes.• Proper isolation been done between Digital and RF sections at various stages in order to provide high RF performance and to avoid phase noise & High EVM issues. Show less
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  • Qnu Labs
    Senior Hardware Security Specialist (Technical Lead Hardware Design Engineering)
    Qnu Labs Dec 2019 - Feb 2021
    Bangalore
    • Worked on complete RF Analog and Digital Hardware PCB Design of Single Photon Detector (SP-QKD) System with the target of achieving 50% photon detection efficiency at 10ns detection dead time with Gating Frequency of 1GHz.• Hardware architecture consisted of multiple RF Analog and Digital boards with the purpose of achieving scalability, flexibility, modularity, noise reduction, efficiency, ease of debug.• Ensured that BOM engineering takes care of High-volume manufacturing… Show more • Worked on complete RF Analog and Digital Hardware PCB Design of Single Photon Detector (SP-QKD) System with the target of achieving 50% photon detection efficiency at 10ns detection dead time with Gating Frequency of 1GHz.• Hardware architecture consisted of multiple RF Analog and Digital boards with the purpose of achieving scalability, flexibility, modularity, noise reduction, efficiency, ease of debug.• Ensured that BOM engineering takes care of High-volume manufacturing requirements such as low cost, high component availability, compactness, manufacturability, low power consumption and thermal efficiency.• Built strategies to protect the system from various QKD attack scenarios by external intrusive Eve systems after thorough study of various research papers by the team on the subject, discussion of those research papers and implementation of solutions in Hardware to counter those attacks.• Worked with various cross functional teams to ensure that a flexible and efficient FPGA and software Architecture is put in place.• Involved in planning/execution of the various activities related to the building of the product prototype such as Research Work, Hardware Design, FPGA Design, Software Design, Simulation, Mechanical Design, Module level testing and Integrated System Testing. Show less
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  • Broadcom Limited
    R&D Engineer - Ic Design 4
    Broadcom Limited Jun 2007 - Oct 2016
    Bengaluru Area, India
    • Worked on design of Validation boards, Reference boards and Characterization boards for various flavors of Broadcom’s XLR/XLS/XLP/Vulcan series of Multi-Core Multi-threaded MIPS and ARM processors and Knowledge Based Processors (KBP).• Interfaces on boards may consist of upto 8x RGMII/SGMII, XGMII, 24x SFP/ 6x QSFP, 2x XAUI/RXAUI/XLAUI, 16-lane PCIE, PCI-X 64/32 bit, PCMCIA, Serial RapidIO, ICI, HyperTransport, SPI-4.2, SATA, USB 2.0/3.0, DDR2/3/4, NAND/NOR Flash, I2C, SPI… Show more • Worked on design of Validation boards, Reference boards and Characterization boards for various flavors of Broadcom’s XLR/XLS/XLP/Vulcan series of Multi-Core Multi-threaded MIPS and ARM processors and Knowledge Based Processors (KBP).• Interfaces on boards may consist of upto 8x RGMII/SGMII, XGMII, 24x SFP/ 6x QSFP, 2x XAUI/RXAUI/XLAUI, 16-lane PCIE, PCI-X 64/32 bit, PCMCIA, Serial RapidIO, ICI, HyperTransport, SPI-4.2, SATA, USB 2.0/3.0, DDR2/3/4, NAND/NOR Flash, I2C, SPI, UART.• Worked on around 8 boards of different complexities with a maximum stack-up of 24 layers.• Max 22 numbers of dedicated power supplies (ATX, VRMs, LDOs and Switching regulators) were used for testing the various rails of the processor.• Designed boards based on ATX, PCIE and OCP form factors.• Work involved Feasibility study, Design Documentation, Circuit Design, Components selection, OrCAD Schematics Entry, BOM release, Allegro layout support, Signal Integrity Analysis, EMI/EMC compliance, Board bring-up, Testing using Multi Meters, Oscilloscope, Function Generator, Logic Analyzer, Thermal Chamber testing.• Reviewed multiple customer schematics and layout for ensuring compliance with Broadcom’s design requirements and help the customers in reducing their product lifecycles.• Studied various Open Compute Project (OCP) architectures in order to implement Datacenter based Hardware architecture for Broadcom's ARM based Vulcan processor. Show less
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  • Anveshan Telecom
    Technical Manager
    Anveshan Telecom Mar 2006 - Jun 2007
    Bengaluru Area, India
    • Worked on DSP/Packet Control Card used for both DSP as well as Packet processing applications.• It comprised two of Freescale’s Quad Core MSC8144 DSP processor and two Virtex-5 FPGAs. • The board had multiple DDR2 SDRAMs connected to the FPGA to be used as Frame, Control, Search and Statistics memory for Packet Processing. The two FPGAs were connected through multiple Serial interfaces. There were Octal 10/100 Ethernet and 28 channel E1 interfaces connected to the backplane. Also 1.25… Show more • Worked on DSP/Packet Control Card used for both DSP as well as Packet processing applications.• It comprised two of Freescale’s Quad Core MSC8144 DSP processor and two Virtex-5 FPGAs. • The board had multiple DDR2 SDRAMs connected to the FPGA to be used as Frame, Control, Search and Statistics memory for Packet Processing. The two FPGAs were connected through multiple Serial interfaces. There were Octal 10/100 Ethernet and 28 channel E1 interfaces connected to the backplane. Also 1.25 Gig serial interfaces were connected to the backplane from Virtex-5 RocketIO.• The card was designed in a Double-width Half-height AMC form factor which could be jacked into an ATCA carrier card.• Work involved Chipset selection, Schematic Design review, Layout Guidelines/review. Show less
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  • Telsima
    Hardware Engineer
    Telsima Jan 2005 - Feb 2006
    Bengaluru Area, India
    • Worked on Multi-service card capable of framing and mapping both telecom and datacom traffic into SONET/SDH transport payloads. On the line side, Multi-service card supported protected OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 interfaces. On the client side, 6 X Fast Ethernet (10/100) Mbps, 2 X 1Gig Ethernet and 24 X DS1/E1 interfaces were available.• The VersaNode and MSF2500 chipsets of Galazar Networks formed the core of the Multi-service card which supported all these interfaces and… Show more • Worked on Multi-service card capable of framing and mapping both telecom and datacom traffic into SONET/SDH transport payloads. On the line side, Multi-service card supported protected OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 interfaces. On the client side, 6 X Fast Ethernet (10/100) Mbps, 2 X 1Gig Ethernet and 24 X DS1/E1 interfaces were available.• The VersaNode and MSF2500 chipsets of Galazar Networks formed the core of the Multi-service card which supported all these interfaces and perform all the SONET/SDH section and line terminating functions. This card also contained Freescale’s MPC8360 processor which performs system controlling and Management functions as well as processing of ATM and Frame-relay traffic coming on the TDM ports.• Work involved Chipset selection, Schematic Design, Layout Guidelines. Show less
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  • Deccanet Designs
    Member Technical Staff To Team Leader
    Deccanet Designs Oct 2000 - Jan 2005
    Bengaluru Area, India
    • Worked on Voice / Fax / Data Multiplexer product which could compress four 4 Wire E&M analog channels, a V.24 asynchronous data channel and a V.24 synchronous channel into a single 64 kbps stream at V.35 interface. The voice on each analog channel could be compressed to selectable compression rates from 2.4 to 9.6 kbps, 16 , 24 , 32 or 40 kbps. Off-the-shelf chipsets such as AudioCodes AC48304 and AMBE-2000 was used for compression and Analog Devices’ ADSP-2181 was used for system… Show more • Worked on Voice / Fax / Data Multiplexer product which could compress four 4 Wire E&M analog channels, a V.24 asynchronous data channel and a V.24 synchronous channel into a single 64 kbps stream at V.35 interface. The voice on each analog channel could be compressed to selectable compression rates from 2.4 to 9.6 kbps, 16 , 24 , 32 or 40 kbps. Off-the-shelf chipsets such as AudioCodes AC48304 and AMBE-2000 was used for compression and Analog Devices’ ADSP-2181 was used for system initialization and controlling operations.• Worked on 4E1-to-1E1 Compression System designed to implement a 120-channel compression system for compressing 4 E1 TDM streams to a single E1 TDM stream. The compression was implemented using a matrix of 30 DSP56311 processors each of which perform Voice compression, echo cancellation and fax/data modulation /demodulation. Apart from the 30 DSP56311s, a 31st DSP56311 performs Signal handling and controlling operations. Spartan FPGA from Xilinx was used for E1 framing/de-framing and multiplex/demultiplexing operations.• Work involved Chipset selection, Schematic Design, Layout support, FPGA design, software design, board bring up, system testing, field trials and hw/sw/fpga team leadership/coordination. Show less
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Sameer Shaikh Education Details

Frequently Asked Questions about Sameer Shaikh

What company does Sameer Shaikh work for?

Sameer Shaikh works for Hfcl Limited

What is Sameer Shaikh's role at the current company?

Sameer Shaikh's current role is General Manager (Head of Hardware Engineering, 5G Business).

What schools did Sameer Shaikh attend?

Sameer Shaikh attended Manipal Institute Of Technology, St. Aloysius College, Mangalore-575003, St. Anthony's High School, Hyderabad.

Who are Sameer Shaikh's colleagues?

Sameer Shaikh's colleagues are Shubham Manger, Gopesh Kaushik, Harish Kumar, Sunil Kumar, Ganesh Chaudhari, Tarun Kumar, Praveen Banala.

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