SENIOR ENGINEERING EXECUTIVE WITH 15 YEARS OF EXPERIENCE IN SEMICONDUCTOR CHIP DESIGN VERIFICATION (DV), COMMUNICATION TECHNOLOGIES AND SOFTWARE/HARDWARE SOLUTIONS INTEGRATION.• 15+ years of experience as an Digital ASIC Designer performing the RTL Design/Coding and Chip Level Verification at RTL and Gate Level• Expert in Client Engagement for Process and Operational Excellence Initiative drive• Expertise in SoC (System on Chip) Level Verification using Cadence AHB/APB Verification Models and MIPS OCP BFM• Had motivated, monitor and lead teams of up to 5 Direct Reports with over 3 Indirect Reports• Performed duties as an Onsite Coordinator during the period of 6 years in South Korea and locally at India• Expertise in Organization Branding through Publication, Patents and Trademarks• Well versed with Customer Account Planning and Management Techniques• Involved in 4+ First Pass ASIC Tapeouts and 2+ FPGA Prototyping• 4 years of expertise in complete product development from requirement elicitation to product integration for an Internet of Things(IoT) / Machine-to-Machine(M2M) solution• Deep Exposure to Start-up culture and performed duties as an Product Research and Development, EMS Manufacturing, Sales and Marketing and Customer Support