Samir Chitnis Email & Phone Number

Santa Clara, California, Us

Santa Clara, Ca, Us

RTL design team member for ThunderX ARM core.

Santa Clara, California, Us

Santa Clara, California, Us

Santa Clara, Ca, Us

Working on Load-Store unit RTL

Santa Clara, California, Us

RTL team member of out order execution and retirement unit for K12 ARM core. Apart from writing logic in Verilog:- Worked with physical design team on RTL changes needed for timing closure. - Did power analysis and worked on solutions to improve power.

Santa Clara, California, Us

RTL team member of out order execution and retirement unit for K12 ARM core. Apart from writing logic in Verilog:- Worked with physical design team on RTL changes needed for timing closure. - Did power analysis and worked on solutions to improve power.

Santa Clara, California, Us

RTL team member of out order execution and retirement unit for K12 ARM core.

Santa Clara, California, Us

Functional Verification of Execution and Scheduling unit of bulldozer core:- Develop and maintain C++ testbench components : checkers, monitors and fake models for other units.- Develop and maintain System Verilog checkers.- Write Assertions in System Verilog and Coverage in System Verilog and C++.- Unit and core level RTL debug using waveform tools.- Test planning for various micro-architectural features. Core Level Functional Verification:- Test planning for core level features. - Write directed tests in x86 assembly language.

Los Angeles, Ca, Us

Grader for courses taught by: Prof. Gandhi Puvvada and Prof.Monte Ung.Responsibilities: - Grading the homeworks and exams.- Help the students with the course work.Graded following courses: - Computer Systems Organization (EE457): Register transfer level machine; organization and detailed implementation of non-pipelined and pipelined processors; cache and virtual memory-Introduction to Digital Circuits(EE201): Verilog-based design, simulation, and implementation in FPGA; timing analysis; simple CPU design; Synchronous design of datapath and control-Introduction to Digital Logic (EE101): Boolean function synthesis; combinational logic devices; sequential circuits; state machine design and implementation.

Charlotte, North Carolina, Us

- Programming of control logic and human machine interface for DCS and PLCs.- Designing the hardware configuration and connection diagrams for DCS and PLC. - Preparing design documentation for DCS and PLC projects. - Onsite support for plant commissioning activities.- Project co-ordination with front office engineers in Europe.

- Part of the committee that designed the project wide standards (control and human machine interface) for batch processing.- Design Engineering for oil refinery project. - Design and document the standards for control loops.

M.S., Computer Engineering

Bachelor Of Engineering, Electrical Engineering