Samir Chitnis

Samir Chitnis Email and Phone Number

CPU Core RTL Design at AMD @ AMD
Sunnyvale, California
Samir Chitnis's Location
Santa Clara, California, United States, United States
About Samir Chitnis

CPU RTL design engineer with experience on out of order execution unit and Load-Store unit. Also worked on DV for out of order execution unit.

Samir Chitnis's Current Company Details
AMD

Amd

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CPU Core RTL Design at AMD
Sunnyvale, California
Website:
amd.com
Samir Chitnis Work Experience Details
  • Amd
    Cpu Core Rtl Design
    Amd Nov 2020 - Present
    Santa Clara, California, Us
  • Marvell Semiconductor
    Cpu Core Design Engineer
    Marvell Semiconductor Oct 2019 - Nov 2020
    Santa Clara, Ca, Us
    RTL design team member for ThunderX ARM core.
  • Intel Corporation
    Rtl Design Engineer In Configurable Fabrics Group
    Intel Corporation Jan 2019 - Sep 2019
    Santa Clara, California, Us
  • Intel Corporation
    Cpu Rtl Design Engineer
    Intel Corporation Sep 2016 - Jan 2019
    Santa Clara, California, Us
  • Soft Machines
    Staff Engineer
    Soft Machines Apr 2016 - Sep 2016
    Santa Clara, Ca, Us
    Working on Load-Store unit RTL
  • Amd
    Member Of Technical Staff
    Amd Jul 2015 - Mar 2016
    Santa Clara, California, Us
    RTL team member of out order execution and retirement unit for K12 ARM core. Apart from writing logic in Verilog:- Worked with physical design team on RTL changes needed for timing closure. - Did power analysis and worked on solutions to improve power.
  • Amd
    Senior Design Engineer
    Amd Jul 2013 - Jun 2015
    Santa Clara, California, Us
    RTL team member of out order execution and retirement unit for K12 ARM core. Apart from writing logic in Verilog:- Worked with physical design team on RTL changes needed for timing closure. - Did power analysis and worked on solutions to improve power.
  • Amd
    Design Engineer 2
    Amd Feb 2013 - Jun 2013
    Santa Clara, California, Us
    RTL team member of out order execution and retirement unit for K12 ARM core.
  • Amd
    Design Engineer 2
    Amd Nov 2010 - Jan 2013
    Santa Clara, California, Us
    Functional Verification of Execution and Scheduling unit of bulldozer core:- Develop and maintain C++ testbench components : checkers, monitors and fake models for other units.- Develop and maintain System Verilog checkers.- Write Assertions in System Verilog and Coverage in System Verilog and C++.- Unit and core level RTL debug using waveform tools.- Test planning for various micro-architectural features. Core Level Functional Verification:- Test planning for core level features. - Write directed tests in x86 assembly language.
  • University Of Southern California
    Grader, Computer Architecture And Logic Design Courses
    University Of Southern California Jan 2009 - Nov 2010
    Los Angeles, Ca, Us
    Grader for courses taught by: Prof. Gandhi Puvvada and Prof.Monte Ung.Responsibilities: - Grading the homeworks and exams.- Help the students with the course work.Graded following courses: - Computer Systems Organization (EE457): Register transfer level machine; organization and detailed implementation of non-pipelined and pipelined processors; cache and virtual memory-Introduction to Digital Circuits(EE201): Verilog-based design, simulation, and implementation in FPGA; timing analysis; simple CPU design; Synchronous design of datapath and control-Introduction to Digital Logic (EE101): Boolean function synthesis; combinational logic devices; sequential circuits; state machine design and implementation.
  • Honeywell Automation India Limited.
    Engineer
    Honeywell Automation India Limited. Jul 2006 - May 2008
    Charlotte, North Carolina, Us
    - Programming of control logic and human machine interface for DCS and PLCs.- Designing the hardware configuration and connection diagrams for DCS and PLC. - Preparing design documentation for DCS and PLC projects. - Onsite support for plant commissioning activities.- Project co-ordination with front office engineers in Europe.
  • Honeywell, United Kingdom
    Engineer
    Honeywell, United Kingdom Oct 2007 - Mar 2008
    - Part of the committee that designed the project wide standards (control and human machine interface) for batch processing.- Design Engineering for oil refinery project. - Design and document the standards for control loops.

Samir Chitnis Skills

Verilog Systemverilog Vhdl C++ Fpga Computer Architecture Functional Verification Logic Design Microprocessors Control Systems Design Debugging Digital Signal Processors Integrated Circuit Design Simulations Processors Static Timing Analysis Digital Electronics X86 Assembly Rtl Verification Uvm Microcontrollers Field Programmable Gate Arrays System Verilog Rtl Design Rtl Coding

Samir Chitnis Education Details

  • University Of Southern California
    University Of Southern California
    Computer Engineering
  • University Of Mumbai
    University Of Mumbai
    Electrical Engineering

Frequently Asked Questions about Samir Chitnis

What company does Samir Chitnis work for?

Samir Chitnis works for Amd

What is Samir Chitnis's role at the current company?

Samir Chitnis's current role is CPU Core RTL Design at AMD.

What is Samir Chitnis's email address?

Samir Chitnis's email address is si****@****hoo.com

What schools did Samir Chitnis attend?

Samir Chitnis attended University Of Southern California, University Of Mumbai.

What are some of Samir Chitnis's interests?

Samir Chitnis has interest in Kindle, Bollywood, Coffee, Design, Nfl, Physics, Football (Us), Computer Science, Science, Education.

What skills is Samir Chitnis known for?

Samir Chitnis has skills like Verilog, Systemverilog, Vhdl, C++, Fpga, Computer Architecture, Functional Verification, Logic Design, Microprocessors, Control Systems Design, Debugging, Digital Signal Processors.

Who are Samir Chitnis's colleagues?

Samir Chitnis's colleagues are Tatum Hartwig, Antonio Chaides, Victor Spiewak, Jovan Mihajlovic, Jessie Gao, Biping Wu, Bala Sai Kosuri.

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