Samir Kagadkar Email & Phone Number

San Jose, Ca, Us

Santa Clara , Ca, Us

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Austin, Texas, Us

Architected, built and maintained the “Tesla tidyflow” - our in-house silicon implementation and sign-off platform. Flows and methodology for everything from design entry-to-tapeout: RTL-to-gates synthesis, place-and-route, multi-point clocks, layout extraction, physical rule checks, layout-vs-schematic, timing analysis and design sign-off.Tidyflow helps crank out high-performance autopilot silicon with high designer productivity.Also led physical design of the processor core that forms the heart of our upcoming ML/AI-accelerator chip.

Cupertino, California, Us

Palo Alto, California, Us

Logic design, physical design, timing closure, design rule checks, physical signoff and chip finishing for Broadcom's flagship datacenter switch chip - the Trident-II+ (BCM56860).Mobile devices, social networking, on-demand video and cloud storage have moved the center of the computing landscape to the datacenter where fast and flat networks connect many tens of thousands of servers to each other. The Trident-II+ chip is the latest in Broadcom's family of Trident rack switches, enabling tomorrow's datacenter communications needs.- Top-level design rule checks (DRC), layout-versus-schematic checks (LVS), signal integrity, antenna checks. Root cause and rectify top-level rule check errors.- Netlist-to-GDSII layouts for three multi-million instance blocks: two blocks on the switch input pipeline and one block on the switch output pipeline.- Timing analysis, ECO generation and block signoff- Logic design for one input pipeline block to enable aggressive timing goals. RTL entry and logic restructuring in Verilog. Re-pipelined error detection and error correction logic along the paths to large banks of memories. Retimed critical timing paths to balance out the work done in each clock cycle, and thus achieve frequency goals.- RTL restructuring for another large block on the switch output pipeline that was previously unroutable. Root caused heavy routing congestion to logic structures in the RTL code. Rewrote RTL code and successfully disentangled these congested modules.

Davis, California, Us

I performed original research in the area of circuit failure prediction under Prof. Al-Asaad. My work included study of device failure mechanisms, including the NBTI effect that primarily affects p-channel MOSFET transistors. In addition I developed strategies for allocating on-chip prediction sensors that will help the early identification of circuit performance problems.I also developed RTL-to-gates synthesis flows for the the many-core processor array chip designed at the Davis VLSI Computational Laboratory (VCL). These flows map abstract design specifications written in Verilog RTL to gate-level netlists in 28nm CMOS technology.Teaching Assistant for several upper-division courses in the Department of Electrical and Computer Engineering:- EEC172: Embedded Systems (Winter Quarter 2012)- EEC118: Digital Integrated Circuits (Spring Quarter 2012)- EEC170: Computer Architecture (Fall Quarter 2012)As part of my Teaching Assistant responsibilities, I led and supervised labs, held tutorials and office hours, as well as graded reports, assignments and examinations. For the Embedded Systems course, I helped students develop ARM microcontroller-based embedded systems, debugged their system-level design issues as well as debug embedded C code.

Palo Alto, California, Us

Physical design, timing closure and sign off of various Broadcom enterprise networking ICs, including:- FP3Core member of Broadcom’s nascent custom ASIC development efforts. We laid out the FP3 network processor for Alcatel-Lucent - it was hailed the industry’s first 400Gbps-capable network processor. I was responsible for all physical design aspects of FP3’s massive control plane processor:Floorplanning, Placement, Congestion relief, Clock tree synthesis, Routing, DRC and LVS analysis/fixes, Power and Signal Integrity verification, Timing closure and Chip finishing.- BCM56440I led full-chip timing closure activity for various modes of operation of the 56440 mobile backhaul switch chip. Was responsible for full-chip static timing analysis, timing ECO generation and final design sign-off. I implemented some cool techniques that resulted in peak voltage drop reduction. I also placed-and-routed a medium-sized memory manager block.- BCM56330Block-level place-and-route, timing closure and design sign off of this enterprise switch IC.

Dallas, Tx, Us

I worked as a Physical Design engineer on various application-specific integrated circuits (ASICs).The first chip project I worked on was the TNETW1350 - an integrated WiFi a/b/g solution featuring a media access controller (MAC), baseband processor and on-chip analog radio. It was used in WiFi access points and was often bundled with TI’s DSL modem products as a residential gateway. I worked on all aspects of the chip design process starting from gate-level net list to detailed GDS layout. Tasks included full-chip flat place-and-route, clock tree construction, power integrity analysis, signal noise fixes as well as timing closure and sign off. Post tape-out and sampling the 1350, I identified targeted layout edit operations for Focused Ion Beam (FIB). FIB is similar to electron microscopy and allows the careful deletion and addition of metal wiring material from a fabricated IC by aiming ions at targeted locations of the chip. My edits reconfigured coefficients of hardwired digital filters on the chip. We rewired a number of coefficients - flipping the bits from 1s to 0s and vice-versa. After testing and verifying the parts, we proceeded to ECO (Engineering Change Order) and re-spin the 1350.I also went on to work on a few more chips at TI. These were mainly ARM-based imaging co-processors featuring dedicated still and video accelerators that focused on the burgeoning camera phone market. I handled RTL-to-gates synthesis, formal equivalence checking, static timing analysis, ECO generation, fixing timing violations - all in addition to my core physical design responsibilities.Tool Expertise: Synopsys Design Compiler, RTL Compiler, Magma BlastFusion/Talus, IC Compiler, Azuro Powercentric/Rubix, Synopsys PrimeTime SI, Verplex LEC, Formality

Master Of Science (M.S.), Electrical And Computer Engineering

B.Tech., Electrical Engineering