• Explored a novel digital clocking source IP for guard-band reduction.• Ground-up design to pre-layout stage using latest technology generation. Considered latest existing techniques internally and from literature to design and characterize custom-digital portion of design. • Wrote ground-up Verilog to represent digital (controller) portion of design and show performance ofthe pre-layout combined system in mixed-signal simulation.

• Analyzed digital clock safety IP to validate performance under challenging fault conditions.• Original scope of project was simulations; completed extensive simulations and added an analysis of clock domains to identify and rule-out plausible failure modes and suggest future directions for IP.

• Wrote complete data migration system in Java in Eclipse IDE using the IBM Notes API and the Java SAX parser to translate loosely formatted Lotus Notes database documents into import-ready CSV files for the Atlassian JIRA issue tracking software. o This project resulted in the successful importation of over 1,500 bug reports. Over 5,000 attachments and inline images were extracted, decoded, and seamlessly reinserted into their containing reports during this process, while rich-text features such as colored text were preserved through a successful conversion of proprietary source XML to wiki markup.o The usability of the CSV files was ensured through DevOps-style real-time cooperation with another engineer and a JIRA specialist through the entire export and import process.• Built and documented an automated system to manage .msi and Java software installations and updates on small network of windows computers using batch files and PowerShell scripting.• Attended daily Agile stand-up meetings with professional software team to discuss items such as releases, blocking issues, and development sprints.