Giving webinars and online training in VLSI design and verification for freshers, engineering students.The position is contractual on pay/hr basis.

With over six years in social service and project management, I excelled at ISKCON Govardhan Eco Village, leading Agile Scrum and Lean Six Sigma initiatives. I specialize in coaching, training, and facilitating diverse teams, optimizing processes, and enhancing efficiency.Key Achievements:Scrum Master and Agile Project Manager for Software Team- Guided a 5-member team to develop a Temple Management System using Scrum.- Managed project backlogs, maintained a Scrum board with Jira, and collaborated with stakeholders for product quality and goal alignment.- Developed features like congregation management (June 2018 - Sept 2019), event management (Oct 2019 - Oct 2020), library management (Nov 2019 - May 2020), and accounting (June 2020 - Sept 2024).Scrum Trainer for Diverse Teams- Coached teams on Scrum principles and Trello for enhanced productivity.- Trained construction teams in backlog creation, sprint planning, and retrospectives.- Guided book production teams and educational teams in adopting Scrum.Lean Six Sigma Process Optimization Across Departments- Applied DMAIC methodology to optimize operations in farming, construction, carpentry, and the community kitchen.- Developed automated tools for labour payment, production tracking, distribution management, and manpower allocation for enhanced efficiency and accountability.These achievements enriched my skills and left a lasting impact on the organization.

• Project 4: Scope: TII (Technology Innovation Initiative) Project for Imaging based Vibration Analysis.(Jan. 2014 to March. 2015)- Role: Worked on FPGA development on the TII idea project which received an approval& funding from the global committee. The algorithms were developed & simulated initially in SCILAB & then gradually were developed and verified in FPGA.•Project 5: ADAPT.ESD Product Sustenance(Jan 2015 to Mar 2016).- Role: Worked on resolving the CIR cases with enhanced algorithms to reduce the noise sensitivity of speed measurement algorithm. Added internal debug features to capture and analyze the internal data, statuses. Contributed for testing for 1.1 release regression cycle. • Project 6: FPGA Development on NGP (Next Generation Batch Controller)(May 2015 to Mar 2016).- Role: Completed design of basic FPGA framework. Designed PERL script to auto-generate top module. Worked on integrating UART module to FPGA.• Project 7: FPGA Warning fixes for IEEE-488 CAN FIFO project.(Dec 2015 to Jan 2016).- Role: Involved in Third Party Review-TPR of the VHDL FPGA code for analyzing & fixing synthesis warnings for this project.Other Responsibilities and Achievements:• Completed the General Electric's ACE B- Course curriculum on Control System Engineering and participated in Software Tear Down Training and Oil & Gas Familiarization Course at Nuovo Pignone, Florence, Italy from 5th May 2014 to 16th May 2014.• Took part in Health-Ahead Wellness Committee at GE O & G MTC (Mumbai TechnologyCenter) to represent the "Stress & Non-Physical Health" element. Suggested different initiatives toreduce the stress level and improve non-physical health of employees.

• Project 1: FPGA & Firmware Development on ADAPT.BHM (Blade Health Monitoring) (May 2011 to Sept 2011)- Role: Worked on improvements of TOA (Time of Arrival) algorithm inside FPGA. Completed the TPR (Third Party Review) of BHM FPGA code for release 2.0. Worked on some firmware Tasks. • Project 2: FPGA & Firmware Development on ADAPT.ESD Product (IEC 61508 - SIL3 Certified)(Oct. 2011 to Dec. 2014)- Role: Contributed to deliver ADAPT.ESD (Emergency Shut Down System ) 1.0 release for Gas Turbines by participation in development & testing phases: multiple manual regressions, identifying bugs and fixing them etc. The FPGA design was made to be IEC61508 - SIL3 compliant. Developed Verification Suit for ESD FPGA system with 100% Branch coverage. Also Involved on various aspects to make ADAPT.ESD project ready for Safety Integrity Level 3 Certification Audit. This involves: > Worked on Action Items Suggested during SIL3 pre-audit by Excida. > Technical Writing: Documents related to ESD FPGA - Architecture & Design , Maintenance Manual, Development Methodology, Hardware Debugging Techniques, Test Verification Suit, > Worked on FPGA-EDA Tools Qualification HAZOP Analysis.Project 3: Six Sigma Green Belt Project – Relay Controller Solution for multiplexing function generators.(Dec 2011 to Dec 2012)- Role: Worked on development of 8 channel Relay Board with opto-isolators controllable by parallel port of the PC. Developed the TCP-IP server & client GUI applications to control the relays remotely over Ethernet to multiplex the FGen signals. This reduced number of function generators required in the lab for testing saving significant cost.Other Responsibilities & Achievements:-Worked on Firmware Development using C++ targeting QNX application on PowerPC. - Followed Agile Product Development Methodology. - Completed Six Sigma Certification with a Green Belt Project- Completed GE's ACE- A course in Software Engineering with 83.80% in 2013.

- Conducted practical sessions on 8051 micro-controller programming. - Delivered lectures on semiconductor fabrication steps - processes (component device & technology). - Guided student groups on academic projects based on SOC design in FPGA using picoblaze microcontroller & embedded system design with 8051.

• Project: Computer Vision Based Offset Error Computation for Web Printing Machines using FPGA.Roles:- Proposed a new efficient Registration Mark pattern for CMYK printing process and designed an offset error computation scheme for it, which can compute not only horizontal & vertical positional offsets but also angular offset with direction inside FPGA. - FPGA Based System Designed in Verilog which includes: 2D convolution (with selectable edge detection filter from Sobel horizontal, Sobel vertical, Laplacian, LOG, etc.), Bayers Interpolator, RGB to Y (Luminace)/Gray conversion, Camera link interface, & I2C Master modules, Offset Error Compute module, CORDIC algorithm.- The Test Bench Suit Designed in Verilog which includes: Simulation model of Micron CMOS Image Sensor with it’s pixel data interface & I2C slave interface, Simulation model of System Board, design of modified VPI tasks using opencv commands to read, write & display image through simulator window. - Extra Assignments: Also studied various video compression codec algorithms & implemented an intercoding part (i.e. JPEG) in Matlab.

• Project: PCI Express FPGA (Virtex5-LXT) based Hardware Accelerators.Roles:- Migrated the older design which was having compression IP cores (owned by INDRA Networks) in multiple Virtex4 PCIX FPGAs into a single Virtex5 FPGA with inbuilt PCI express hard IP core & pcie endpoint block plus wrapper solution.- Studied the pcix & pcie protocol and involved in fixing the design goals.- Worked on PCI Express Transaction Layer Interface of endpoint block plus IP and was involved in RTL design & verification in Verilog, which includes design of Initiator & Targets, Rx & Tx machines at TL Interface and development of test bench & test cases.- Parameterized the whole design using efficient coding style to make it flexible; which has given ability to change number of compression cores from 1 to 8 by simply changing parameters which has saved the future design times & efforts.

Worked in WLAN Engineering department in MAC group. Involved in RTL Verification activities.• Project: WLAN - MAC IC (IEEE802.11n standard.)- Role: Worked on RTL Verification of CCMP (AES encryption) & DMA modules in Base-band Interface subsystem. Worked on Debussy tool to set the environment to compile & elaborate the mixed language database/RTL files. Learned Perl & used it to write various supporting scripts.