Sandeep Chikkerur Email & Phone Number

Bengaluru, Karnataka, India

Bengaluru Area, India

* Feature requirements, design and impact analysis on the overall system - Nexus switches* Complete ownership of complex FHRP, ACL components on Cisco Nexus Switches* Sr. Customer Escalation Lead for highly complex customer issues * Responsible for component quality issues, hardening plans* Release road maps planning, owning the scrubber for releases* Excellent Technical Documentation skills

Development of SNMP Infra on Cisco's Nexus-7K series of switches.• Complete ownership of SNMP component• Handling customer cases including escalations• Feature developments, improvements • Technical lead in front ending every issue, mentoring• Member of MIB Review committee• Engineering excellence award for designing the SNMP infra architecture as POC to support OS Harmonization project

Bangalore

Managed and technically architected the EPC and SGSN (PreR8) simulator development to test the Core LTE EPC network entities (MME/SGW/PGW) covering 3GPP Release-8 to Release-9. S1AP/GTPv1/v2 and GTPU stacks are supported. Supported Features - functional and performance/capacity testing, DHCPv4/v6 client functionality, NAS security, inter RAT HO, Data Path support etc. * Client interaction, discussion on the proposal scope for important features and 3GPP LTE adaptation* Responsible for all the deliverables* Onsite Technical Team Leader (South Korea, Apr 2011 To Jan 2012) * Lead the team of 10 engineers

Technical lead in developing EPC and SGSN (PreR8) simulator to test the Core LTE EPC network entities (MME/SGW/PGW) covering 3GPP Release-8 to Release-9. S1AP/GTPv1/v2 and GTPU stacks are supported. It provides features for describing the logic of the test cases as well for creating and updating the message templates. Features include - functional and performance/capacity testing, DHCPv4/v6 client functionality, NAS security, inter RAT HO, Data Path support etc. Contribution:• LTE EPC and SGSN Call Simulator framework design, coding• Call context and Data Path(open source) design• Feature enhancement of the simulators• Development of SGSN simulator• Requirement analysis, Design documents• Automation of system integration testing* Involved in ISO CMMi Level 5 v1.2 company wise audit program

Bengaluru Area, India

Responsibilities and contributions - GSM Mobile Handset * Implementing interrupt kernel, Channel Coding for DSP Physical layer for GSM mobile handset* Porting of channel coding on Analog Devices 218x, TI's 54x boards* Integration of entire protocol stack on Sasken's framework ARIA* Implementation/Porting of Channel Coding (FR, HR, EFR) in 218x Assembly* Unit and Integration Testing* Optimization of the channel codecs to 60% of the reference codecs* Loop back testing of Speech Codecs with channel codecs * System Debugging (Using HSL and/or Lauterbach) on RACAL and Agilent* AMR voice call integration* Interaction with the Protocol Stack team during integration of L1 DSP* Implemented Performance related module for memory utilization in C* System level debugging and bug-fixing* Debugging of modules ranging from File System level to MMI modules

Bangaon Area, India

RSE is Restraint System Electronics. RSE involves Crash Sensing Algorithms for vehicles. These algorithms decide if the AIRBAGS have to be deployed or not depending on the severity of crash. The different crash sensing algorithms are developed for Front, Side, and Roll Over crashes. The simulation tool for the same is developed and it is tested with different crash data obtained by crashing the vehicles. Depending upon the test results, the algorithm parameters are calibrated so that the results obtained from the simulation match the on-field results. Contribution:* Simulation Code walk through of different crash sensing algorithms * Enhance the simulation code for the issues obtained during the on-field testing and depending on calibration settings in C language* Development of New algorithm for both Frontal and SDM (Sensing & Diagnostic Module)* Crash Data Analysis

Bengaluru Area, India

The code converter translates assembly code from one DSP architecture to another DSP architecture. The translator accepts mnemonic assembly as input. Important features of code converter include support of circular, bit reversal buffers, Assembler directive translation, macros support, ABI convention handling etc. The entire project has been implemented in C. • Study of both the Teak ,CEVA1620, ZSP400, ZSP500 DSP architectures.• Developed the assembly instruction mapping set for Teak to CEVA1620 code • Testing of the mapped code on both the DSP simulators• Implementation of Front End (Parser)• Implementation of Loop Invariant Code Motion - This needed the understanding of how to identify the definition registers Implementation of Register Allocation - This needed the understanding of the Register sets of both the above architectures• Implementation of address identification - This needed the register set knowledge of both the above architectures • Implementation of test driver generation for instruction level testing - This needed the code walkthrough of the similar test generation driver• Implementation of peephole optimizations -This needed the understanding of the identification of definition and usage of registers

B.E, Electronics And Communications

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