Responsible for testing and evaluating device characteristics of SRAM products across technologies. Worked on several technology designs at once to provide full SRAM characterization at the wafer and product levels for each. Responsible for providing analysis reports and graphs to requesting engineers. Generated test code using SPECS and in house perl based tools. Full device characterization testing and reported on any electrical changes that may have occurred due to process changes, particularly if they were out of spec or affected overall yield. Supported the management of the device test lab which was shared with other departments. Responsible for training all users of the lab in the use of all equipment in the lab. This included 12” EG automatic probe systems, TEL P12 and P12XL automatic probe systems, in house software used to run EG probers, SPECS software, and some first pass debug procedures when tools had problems.Responsible for yearly cost estimates to keep the lab running, explored future tool purchases, worked with vendors to schedule yearly preventative maintenance tasks, yearly vendor contract support renewals, ordered support items such as probe cards, coolant for probers, and miscellaneous parts to keep the lab running smoothly and efficiently. Also assisted in moving the lab from one location to another.

Responsible for testing and evaluating device characteristics of SRAM products. Generated test code using SPECS and in house perl based tools. Graphing and analyzing data to determine if improvements have been made in the process that will affect the end product. Some test equipment used HP4156, Agilent 4060 & 4072 on both TEL and EG probers. Responsible for the set-up and maintenance of device lab tools, including parts order, calibration, & troubleshooting issues. Gained experience with reliability testing and product testing with the use of Teradyne and HP 93K test systems at both the wafer level and product part level. Collaborated with other organizations to meet product deliverables.

Worked as a process integration technician within the NVM device engineering group. Responsible for creating process flows, providing advanced wafer level inspections at various process stages to determine if the desired results were achieved. Used SEM equipment to measure and provide highly detailed images to engineering at various process stages for different portions of the NVM device under process. Also constructed layout of new test structures using IC Graphs and cadence tools.Responsible for testing and evaluating device characteristics of NVM product. Testing included charge to breakdown, stress induced leakage, data retention, SEM inspections as well as other fab and electrical measurements. Generated test code using HPBasic and in-house perl based tools. Graphing and analyzing data to determine if improvements have been made in the process that will positively affect the end product. Some test equipment used HP4156, Agilent 4060 & 4072 on both TEL and EG probers. Set-up and maintenance of device lab tools, including parts order, calibration, & troubleshooting issues. Responsible for moving the device test lab from one location to another. This included working with facilities to schedule shutdown and power up procedures, lab layout planning with electricians, plumbers, tool reps and owners, IT support, and providing costestimates to management. Proper qualification and start up procedures followed to ensure minimal down time and accuracy of measurements. Equipment move included manual probe stations, automatic EG probe systems, several individual equipment measurement tools, UV ovens, inspection stations, bake ovens, storage cabinets, and computer work stations.

Responsible for planning and organizing wafer throughput from other areas of the fab in order to maximize cycle time and productivity while still running equipment. Was in charge of managing other operators in the etch area and working with lead operators from other areas of the production environment to effectively work together in meeting our shift cycle time and wafer turns.Also scheduled necessary preventative maintenance events with the equipment maintenance group on all etch equipment. Provided management with daily cycle time reports, identified areas of training improvements needed, and shared personal knowledge with fellow employees by providing cross-training. Also worked closely with process engineers in scheduling time for experiments without disrupting cycle time.

Responsible for tracking in silicon wafers from different areas of the fab and following process flows. This entailed running silicon wafers through several different pieces of etch equipment, rinse, bake, and inspection stations. Was able to learn and become certified on all etch equipment at an advanced rate of learning.