Sandra B Email & Phone Number

VLSI Physical Design Engineer, working on advanced process nodes such as 7nm, 10nm, 14nm, 16nm, and 28nm.Developed and implemented physical design methodologies that improved quality and efficiency for advanced process nodes.Successfully handled multi-million gate designs with varying die sizes and complexities.Experienced in handling RTL to GDSII implementation stages and proficient in various stages ofthe PNR (Place and Route) flow.Knowledgeable in low-power design techniques and their impact on back-end flow.Skilled in design planning, PNR activities, STA, and signoff processes including floor planning, placement, optimization, congestion and density analysis, CTS, routing, sign-off ECO, VCLP, RV, timing caliber, DRC, and LVS.Proficient in using industry-standard EDA tools from Cadence, Synopsys, and MentorGraphics.Proficient in scripting languages such as Perl and TCL.Provided technical guidance and mentored junior engineers for their career development.Possess excellent analytical and problem-solving skills and effective communication and interpersonal skills