• Full custom Digital/Analog Circuit design for DRAM and SRAM Cache products up to 11nm technology in the CMOS and SOI CMOS technology.• Designed SerDer (Serializer/Deserializer with registers/latches/encoder/decoder), Data IO path, ODT, DLL, Clock Tree, Test Mode logic (DFT), Array Logic cross section, Data Sense Amplifier, Word line pulse generator, Command State Machine, Latch/Flip-Flop, Delay logic, Voltage Level translator/shifter, Voltage Band Gap Reference, counter.• Robust design for Power Sensitivity Noise and Jittering improvement on Data IO and DLL Clock path.• Architecture and Floor Planning for full chip and DLL/Clock Tree.• Design Verification and simulation for Full Chip Functionality, Timing Analysis and physical layout.• Yield Analysis and improvement• Characterization and Failure Analysis by using ATE machines on Wafer/Package level.• Extensive knowledge/experience from Design to Wafer/Package Test Production, and Customer Qualification.• Managing Design/Product Engineering teams/Long-term Product Planning team, coordinating among development teams, conducting customer meeting, Technology trend/competitor analysis, and long term Product planning.• Product Development Engineering: Long-term Product Planning, New Product proposal, and SPEC generation
Listed skills include Cmos, Verilog, Circuit Design, Physical Design, and 28 others.