Software Engineering Group Director
Current
Jul 2023 - Present
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Sapan Agarwal Email & Phone Number
Software Engineering Group Director at Cadence Design Systems-- Protium Compiler (FPGA Prototyping/Emulation)
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Cadence Design Systems
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Current company
Role
Software Engineering Group Director at Cadence Design Systems-- Protium Compiler (FPGA Prototyping/Emulation)
Location
Ghaziabad, Uttar Pradesh, India
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Sapan Agarwal is listed as Software Engineering Group Director at Cadence Design Systems-- Protium Compiler (FPGA Prototyping/Emulation) at Cadence Design Systems, based in Ghaziabad, Uttar Pradesh, India. AeroLeads shows a matched LinkedIn profile for Sapan Agarwal.
Sapan Agarwal previously worked as Software Engineering Group Director at Cadence Design Systems and Director Software Engineering at Cadence Design Systems. Sapan Agarwal holds Bachelor Of Technology, Electronics Engineering from Iit-Bhu.
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Profile bio
About Sapan Agarwal
Having 20+ years of experience in development of EDA software tools and models for Soc Architecture Exploration and hardware performance evaluation. Currently managing the Protium(FPGA Prototyping) Software Compiler team at Cadence NoidaSpecialties: C, C++, Assembly Language Programming, Multi Threading, Multi Processing, Processor Architcture, Python, Verilog, FPGA Prototyping
Listed skills include Algorithms, Embedded Systems, Eda, Verilog, and 16 others.
Current workplace
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9 roles
Sapan Agarwal work experience
A career timeline built from the work history available for this profile.
Director Software Engineering
Leading the Protium Noida RnD team for compiler and runtime software development. Looking for domain experts to join the Noida team. Required skill set C, C++, verilog, simulation,FPGA prototyping
Jul 2019 - Jul 2023
Senior Principal Software Engineer
Jan 2016 - Jun 2019
Lead Member Consulting Staff
Hardware Accelerator for Verilog SimulationThe project aims at replacing the current software based simulation to hardware based simulation and achieve ~100X performance improvement. Current simulation tools are software based and are very slow for big hardware designs. This involved development of dedicated hardware solution comprising custom logic.
Mar 2013 - Jan 2016
Technical Specialist
I am associated with the architecture team which is developing Application Processor to be used in mobiles.We are developing software tools for architecture exploration of this processor. The tool helps the architects analyse the bandwidth, memory and mips contribution for different use cases.The tool enables the architects to design complex use.
Feb 2009 - Feb 2013
Senior Software Engineer
I am associated with the architecture team which is developing Application Processor to be used in mobiles.We are developing software tools for architecture exploration of this processor. The tool helps the architects analyse the bandwidth, memory and mips contribution for different use cases.The tool enables the architects to design complex use.
Oct 2007 - Feb 2009
Senior Software Engineer
I was associated with Wireless Infrastructure Division Group where we were developing a new Dynamically Reconfigurable Processor which was meant to perform signal processing algorithms like rake receiver, FFT, FIR, Correlation and others. I was involved in development of system software tools to validate the architecture of this processor and also develop.
May 2005 - Oct 2007
Software Enginner
I was involved in developing a tool named FPGA Architecture Estimator. This tool could estimate the architecture of FPGA of any shape and size(not only rectangular shape). It could also handle L or U shaped FPGA's. My job was to design a new Switch Box topology which would route the signals effectively for all shapes and sizes. Applied for a patent for the.
Jul 2003 - May 2005
Mts
Aug 2002 - Jul 2003
2 education records
Sapan Agarwal education
Bachelor Of Technology, Electronics Engineering
Iit-Bhu
12Th, Science
Wilsonia College
FAQ
Frequently asked questions about Sapan Agarwal
Quick answers generated from the profile data available on this page.
What company does Sapan Agarwal work for?
Sapan Agarwal works for Cadence Design Systems.
What is Sapan Agarwal's role at Cadence Design Systems?
Sapan Agarwal is listed as Software Engineering Group Director at Cadence Design Systems-- Protium Compiler (FPGA Prototyping/Emulation) at Cadence Design Systems.
Where is Sapan Agarwal based?
Sapan Agarwal is based in Ghaziabad, Uttar Pradesh, India while working with Cadence Design Systems.
What companies has Sapan Agarwal worked for?
Sapan Agarwal has worked for Cadence Design Systems, Mentor Graphics, St-Ericsson, Stmicroelectronics Pvt. Ltd, Noida, and Hcl Technologies.
How can I contact Sapan Agarwal?
You can use AeroLeads to view verified contact signals for Sapan Agarwal at Cadence Design Systems, including work email, phone, and LinkedIn data when available.
What schools did Sapan Agarwal attend?
Sapan Agarwal holds Bachelor Of Technology, Electronics Engineering from Iit-Bhu.
What skills is Sapan Agarwal known for?
Sapan Agarwal is listed with skills including Algorithms, Embedded Systems, Eda, Verilog, C, Modeling, Python, and C/C++ Stl.
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