20 Years of experience in the semiconductor industry with Hard Macro IP Physical Design Implementation, Static Timing Analysis, SRAM Memory Design, and Digital Circuit Design with successful contributions for 20+ Tapeouts from 65nm to 3nm including advanced FinFET nodes and patented contributions to semiconductor design for Power Performance Area OptimizationResponsible for Leading physical design Projects/team for RTL-GDS PD Subsystem end-to-end multiple HM IP Implementation for SOC/CPU/GPU/MODEM/DSP/DDR starting from RTL-Synthesis, Floorplan, Power grid (PDN), feed-thru, place and route (PnR), clock tree synthesis (CTS), Parasitic Extraction, STA Timing closure, IR/EM, Power/Signal integrity signoff, Physical verification (DRC/LVS/Antenna/ERC/ SoftCheck) and Netlist Verification checks such as Formal equivalence LEC, Conformal Low Power CLPTechnical direction, guidance, and Support to the engineering team for Timing Constraints and Timing Signoff Checks Such as Setup/Hold/Transition/Min-Pulse-Width (MPW)/Duty Cycle Distortion (DCD)/MaxCap/CrossTalk/Noise, etc Excellent analytical and problem-solving skills to complex technical problems and provided solutions in the right direction Such as Set-up and Hold Contention fix, MPW/DCD Innovative fixes, etc Physical design with exposure to the circuit, logic, low power, high-speed, multi-voltage, Synchronous and Asynchronous Clock Domain Crossing (CDC), Multi-Cycle Path, Latch based Time Borrowing Design, etcIndustry-standard EDA tools like Innovus/Primetime/Redhawk/Calibre/FineSim/Hspice/Virtuoso/StarRC, etc. Strong self-driving ability and winning attitude in Technical/Project management People management, goal setting, assessment, calibration, appraisal, and improvement plan. Collaborated with cross-functional teams across different geographies to drive technical Discussions and executive update to Senior Management at the HLDR/MLDR/LLDR.Scripting knowledge in Tcl/Perl/Shell/Bash Adaptive Voltage Scaling (AVS) Implementation and Methodology include BTI Aging and VMIN Analysis for SensorMethodology to Correlate Pre-silicon Model vs Post-silicon for Design Timing.Level1 and Level2 Cache Memory Subsystem Design for DSP and Modem Core. Multiport Latch Array design technique for SOC Area and Power SavingCustom SRAM memory design Critical Path Analysis Such as Clock to Dout (Clock to Wordline to Sense Amplifier to Dout), Bitcell Analysis for Read Current, SNM, Write Margin, Aging/Non-Aging), etcSTDCELL Library Sequential Cell Circuit Design such as Flops, High-Speed Synchronizer, and FlopTray.