Staff Application Engineer
Current
Feb 2024 - Present
AeroLeads people directory · profile
Saritha T. Email & Phone Number
Physical Design Engineer at Synopsys | Ex Qualcomm | Graduated with Honors
at
Synopsys Inc
1 work email found
@synopsys.com
LinkedIn matched
✓ Verified August 2026
4 data sources
Profile completeness 86%
Current company
Role
Physical Design Engineer at Synopsys | Ex Qualcomm | Graduated with Honors
Location
Sunnyvale, California, United States
Who is Saritha T.? Overview
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Quick answer
Saritha T. is listed as Physical Design Engineer at Synopsys | Ex Qualcomm | Graduated with Honors at Synopsys Inc, based in Sunnyvale, California, United States. AeroLeads shows a work email signal at synopsys.com and a matched LinkedIn profile for Saritha T..
Saritha T. previously worked as Staff Application Engineer at Synopsys Inc and Sr Application Engineer at Synopsys Inc. Saritha T. holds Master'S Degree, Digital Vlsi Design/Physical Design from San Francisco State University.
Company email context
Email format at Synopsys Inc
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*@synopsys.com
68% confidence
AeroLeads found 1 current-domain work email signal for Saritha T.. Compare company email patterns before reaching out.
Profile bio
About Saritha T.
➔ Experience in Synthesis, Physical Design implementation and timing analysis at advanced nodes➔ Instrumental in tapeout of multi million gate designs on 3nm 4nm 28nm and 90nm technology nodes ➔ Worked on RTL2GDS of a cutting edge hardware security research funded by DARPA➔ Good understanding of deep submicron concepts like SI, OCVand MCMM analysis➔ Knowledge on UPFTOOLS/SKILLS:Scripting/Programming Languages : Tcl, Shell, Verilog, CSynopsys Tools : Design Compiler, IC Compiler, Primetime, VCS and Custom Designer, Formality and HSPICECadence Tools : SOC Encounter - Floorplan, Innovous
Current workplace
Saritha T.'s current company
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6 roles
Saritha T. work experience
A career timeline built from the work history available for this profile.
Jan 2023 - Present
Applications Engineer Ii
Working on Physical Implementation and PPA Push for CPU/GPU Blocks
Nov 2021 - Dec 2022
Cpu Physical Design Engineer
Worked on Physical Implementation of CPU Interface block which was part of Snapdragon chip
May 2021 - Oct 2021
Feb 2019 - Apr 2021
Research Assistant /Grad Honor Student
➔Developed a look up table(LUT) soft macro and integrated into ASIC flow➔Fixed setup/hold/clock gating setup and transition violations under various scenarios for a complex ASIC design➔Performed CTS aware Clock gating cells placement and optimization which reduced overall chip power by 5 percent➔Built robust clock trees by creating skew groups, NDR’s and exploring various optimization techniques in ICC tool➔Fixed timing/congestion/IR issues by implementing various optimization techniques and thorough analysis➔Acquired good command on Physical design & Timing analysis concepts and implementation using ICC and Prime Time tools
Feb 2016 - Jan 2019
2 education records
Saritha T. education
Master'S Degree, Digital Vlsi Design/Physical Design
San Francisco State University
Bachelors Of Engineering, Electrical And Electronics Engineering
Anna University Chennai
FAQ
Frequently asked questions about Saritha T.
Quick answers generated from the profile data available on this page.
What company does Saritha T. work for?
Saritha T. works for Synopsys Inc.
What is Saritha T.'s role at Synopsys Inc?
Saritha T. is listed as Physical Design Engineer at Synopsys | Ex Qualcomm | Graduated with Honors at Synopsys Inc.
What is Saritha T.'s email address?
AeroLeads has found 1 work email signal at @synopsys.com for Saritha T. at Synopsys Inc.
Where is Saritha T. based?
Saritha T. is based in Sunnyvale, California, United States while working with Synopsys Inc.
What companies has Saritha T. worked for?
Saritha T. has worked for Synopsys Inc, Qualcomm, No-Company. (Self-Employed.), and Sfsu School Of Engineering ( Necrl Lab).
How can I contact Saritha T.?
You can use AeroLeads to view verified contact signals for Saritha T. at Synopsys Inc, including work email, phone, and LinkedIn data when available.
What schools did Saritha T. attend?
Saritha T. holds Master'S Degree, Digital Vlsi Design/Physical Design from San Francisco State University.
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