Sarosh Azad Email & Phone Number

Santa Clara, California, Us

- Lead/Manage Front End Design teams to deliver SOC building blocks such as AI Engine Array (AIE), Communication Protocols Module (CPM) and Network On Chip (NOC) to multiple parallel SOCs and Physical Design teams within AMD- Lead/manage the Functional Safety Design Methodologies team to provide FuSa process definition, manage FuSa process execution and Assessment participation covering all FPGA and ACAP silicon products.

Chadds Ford, Pennsylvania, Us

San Jose, Ca, Us

Design ownership of Cache Coherent Accelerator Platform Negotiated Power and Performance requirements with Product Planning Led review cycles to crystallize Architecture requirements Aligned overall schedules with Architecture, IP Vendors, Validation, Physical Design teams Performed detailed project planning/tracking using Agile methodology Hired and managed experienced design engineers to perform RTL Design and Integration Aligned stakeholders to drive definition of SW Wizard for product delivery and supported development to providing timely and necessary information and team resources Guided development of automation to get continuous visibility into design activity/size/quality metrics Managed releases of design collateral to downstream teams for own as well as other SOC blocks Evaluated change requests, presented proposals to VP level to facilitate schedule/scope adjustments Developed high level understanding of CHI, CCIX, CMN600, ELA500 and FlexNoc technologies IP from several external and internal teams was integrated Captured DFT requirements, specified solutions to meet DFT and other wafer level test requirements Performed top level architecture and integration for all major sub-blocks including DFT features Product: Everest ACAP Platform

San Jose, Ca, Us

• Interface with FPGA and SOC Architecture teams to resolve high level issues for next generation products• Extract explicit design requirements from various sources and get signoff from stakeholders• Develop micro-architectural specifications to address design requirements• Evaluate ASIC IP from internal and external vendors and provide technical guidance to decision makers• Manage development of custom IP at IP vendors to align development, integration and verification schedules• Integrate and/or manage integration of digital and analog IP• Design AXI/APB interconnect for the SOC using NIC301 and NIC400, and CCI400 IP from ARM• Lead design of custom digital blocks to improve robustness and debug-ability of the SOC Interconnect• Integrate PCIe, SATA, DisplayPort, SerDes and AMS IP blocks into the SOC• Suggest testbench architecture and critical testcases, review test plans and coverage metrics• Lead cross functional team to align design and verification schedules and track progress• Provide timing constraints and exceptions for all blocks owned and contribute to STA and closure• Review documentation, RTL, timing constraints, Lint, CDC and other design quality metrics from peers in preparation for tape-out• Propose ECOs, workarounds and alternatives for late found issues and help stakeholders make decisions• Support lab bring-up of SerDes and other SOC features owned• Contribute to development of customer facing documentation including product errata• Represent SOC Design team at silicon engineering meetings• Hire, train and manage SOC Design Engineers and Interns • Product: Zynq UltraScale+ MPSOC

San Jose, Ca, Us

 Integrated 3rd party transceiver IP into Virtex 6 FPGA by adding configuration logic to offer programmability Verification of IP integrated into the FPGA in all known use modes  Specified timing constraints, evaluated results, modified design to improve timing  Supported physical design, tapeout, silicon validation teams Escalated defects in 3rd party IP to vendor and facilitated metal layer fixes Interface with PCIe team to gather requirements and facilitate creation of PHY solution with PIPE Interface Conducted design and block level verification of various features including Comma Alignment, Dynamic Reconfiguration and Status Interface, RX Phase Alignment, PIPE Interface, CAUI Interface, Resistor Reference Calibration, Control Logic for TX Driver for in-house developed SerDes' Regular updates of SerDes user interface data and timing checks to other teams for integration of SerDes into software design environment Setup Code Coverage Metrics collection for Tapeout Readiness reviews Performed quality checks on top level schematics and supervised fixes Created software model of the transceiver for integration into ISE Software Designed routing blocks to work around FPGA floor-plan limitations Coordinated delivery of Schematics, RTL and other metadata to integration team for multiple tapeouts

San Jose, Ca, Us

• Lead development of micro-architectural specification, design and implementation of major sub blocks of PCI Express IP• Conduct block level design verification, debugging using advanced techniques including insertion of snoopers, assertion checks and coverage points, and seamless integration of blocks into system level design verification and validation environment• Interface with system level verification and validation teams to debug and resolve design issues relating to compliance to the PCI Express Specification• Interface and assist with the Xilinx CoreGenTM team, to integrate and deliver of the Intellectual Property product, within the CoreGen framework.

San Jose, Ca, Us

· Evaluate customer design requirements, estimate man-hours needed and specify technical resources for upcoming projects· Interface with customers to prepare statements of work and develop specifications· Design according to customer specifications including micro-architecture, state machine design and design entry (VHDL, Verilog, Schematic Entry, etc)· Modify and integrate existing IP as per customers' design requirements· Create extensive verification suites to fully test all aspects of the design using Xilinx and 3rd party simulation tools

San Jose, Ca, Us

· Interface with customers, helping them with key technical issues· Resolve technical issues with field engineers and salespeople· Develop training materials for customers· Create designs targeting Xilinx FPGA/CPLDs to facilitate customer debug and to provide reference designs for customers· Participate in Solutions Testing· Serve as the point of escalation for all issues in NA related to the following IP: - PCI / PCI-X / PCI Express - ChipScope - Synthesis

San Francisco, California, Us

· Served as SQA Lead for new projects· Coordinated offshore (India) QA team’s efforts with the build/release schedule toachieve overnight automated regression testing and test plan automation· Helped develop and maintain the company’s defect tracking system· Created and maintained test-plans after analyzing product requirement documents and engineering specifications· Conducted tests on patches and full releases to validate features and functionality· Investigated user-reported problems/bugs· Tracked bugs to resolution by working closely with software developers· Developed, maintained, executed and reported software performance benchmarks for Snapfish’s internet based application

Bs, Computer Engineering

Post Graduate Program, Artificial Intelligence And Machine Learning - Business Applications