Sarosh Azad Email & Phone Number

Santa Clara, California, US

- Lead/Manage Front End Design teams to deliver SOC building blocks such as AI Engine Array (AIE), Communication Protocols Module (CPM) and Network On Chip (NOC) to multiple parallel SOCs and Physical Design teams within AMD- Lead/manage the Functional Safety Design Methodologies team to provide FuSa process definition, manage FuSa process execution and.

Chadds Ford, Pennsylvania, US

San Jose, CA, US

Design ownership of Cache Coherent Accelerator Platform Negotiated Power and Performance requirements with Product Planning Led review cycles to crystallize Architecture requirements Aligned overall schedules with Architecture, IP Vendors, Validation, Physical Design teams Performed detailed project planning/tracking using Agile methodology Hired and.

San Jose, CA, US

• Interface with FPGA and SOC Architecture teams to resolve high level issues for next generation products
• Extract explicit design requirements from various sources and get signoff from stakeholders
• Develop micro-architectural specifications to address design requirements
• Evaluate ASIC IP from internal and external vendors and provide technical guidance to decision makers
• Manage development of custom IP at IP vendors to align development, integration and verification schedules
• Integrate and/or manage integration of digital and analog IP

San Jose, CA, US

 Integrated 3rd party transceiver IP into Virtex 6 FPGA by adding configuration logic to offer programmability Verification of IP integrated into the FPGA in all known use modes  Specified timing constraints, evaluated results, modified design to improve timing  Supported physical design, tapeout, silicon validation teams Escalated defects in 3rd.

San Jose, CA, US

• Lead development of micro-architectural specification, design and implementation of major sub blocks of PCI Express IP
• Conduct block level design verification, debugging using advanced techniques including insertion of snoopers, assertion checks and coverage points, and seamless integration of blocks into system level design.
• Interface with system level verification and validation teams to debug and resolve design issues relating to compliance to the PCI Express Specification
• Interface and assist with the Xilinx CoreGenTM team, to integrate and deliver of the Intellectual Property product, within the CoreGen framework.

San Jose, CA, US

· Evaluate customer design requirements, estimate man-hours needed and specify technical resources for upcoming projects· Interface with customers to prepare statements of work and develop specifications· Design according to customer specifications including micro-architecture, state machine design and design entry (VHDL, Verilog, Schematic Entry, etc)·.

San Jose, CA, US

· Interface with customers, helping them with key technical issues· Resolve technical issues with field engineers and salespeople· Develop training materials for customers· Create designs targeting Xilinx FPGA/CPLDs to facilitate customer debug and to provide reference designs for customers· Participate in Solutions Testing· Serve as the point of.

San Francisco, California, US

· Served as SQA Lead for new projects· Coordinated offshore (India) QA team’s efforts with the build/release schedule toachieve overnight automated regression testing and test plan automation· Helped develop and maintain the company’s defect tracking system· Created and maintained test-plans after analyzing product requirement documents and engineering.

Bs, Computer Engineering

Post Graduate Program, Artificial Intelligence And Machine Learning - Business Applications