Satish Dabbar Email & Phone Number

I am a Verification Engineer with over 4+ years of hands-on experience in Analog Mixed Signal and Design Verification. My expertise encompasses Power Leakage Analysis, AMS connectivity, and functionality checks at the SOC level, along with Functional Verification and Coverage-Driven Verification at both the Sub-System and SOC levels.Currently, I am working at Maxliner Technologies, where I've developed test plans and test benches from scratch, ensuring the seamless connectivity and functionality of complex systems. My background also includes significant experience at Infineon Technologies, where I conducted power leakage analysis and co-simulation for mixed-signal connectivity.I am proficient in HDLs such as Verilog and System Verilog, with a strong command of UVM. I leverage tools like Xcelium, Questasim, ModelSim, Finesim, and Cadence Virtuoso to achieve precise verification results. My experience with protocols such as AHB, AXI, APB, I2C, and SPI further enhances my ability to tackle diverse verification challenges.I am passionate about driving innovation in the verification domain and am eager to explore new opportunities to apply my skills in a dynamic environment.Behavioral Skills

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  Sdm Institute Of Technology (Sdmit) Ujire

  Electrical, Electronics And Communications Engineering