Manage and execute SOC/Block level Tempus STA and Tempus ECO solutions across various projects and design centers in advanced technology nodes.

Design, develop, and evaluate integrated circuits for electronic design tools. Responsible for all backend physical design tasks for SOC design using CMOS technologies (16nm, 28nm, 40nm), including logic synthesis, Conformal ECO, Conformal LEC, Floor planning and Power planning, placement and routing, timing optimization , ECO generation, signal integrity analysis, and physical, electrical using complete Cadence flow.

Developed grounding scheme by considering the EMI/EMC effects using NASCAP (NASA Spacecraft Charging Analysis Program) and developed test procedures for satellite subsystems in Indian Space Research Organization (ISRO).