Satish Devarapalli Email & Phone Number

Over 22 yrs of experience in Design verification and Emulation of ASICs/SoCs : Signal Processing based(Touch, Display), Networking Switches, GPS, WiFi-BT Combos, MFP and video decoder set-top box solutions.Architecting Test benches(Block, Full Chip, Multi-Chip)Manage & Lead DV/Emulation efforts for complex SoCs, Verification activities Interface to Customers(Fortune 500 to startups), and EDA vendors. Create schedules, Test Plans, and Test Bench. Mentor junior engineers. Create clear tasks for the team and ensure the team succeeds in results. Responsible to review team member progress and setting them on a path to success. Track status and report progress to exec teams within the organization and to the customers. Ability to play various roles as Managing Global Teams/Verification Lead/Mentor/Team player with a versatile perspective and approach(thanks to UC Berkeley project management courses)Hands-on expertise in developing Test benches, and creating test plans for complex systems.A vision towards verifying actual functionality/applications of the system. Strong desire for achieving the best quality of the product through Functional sims, Assertions, Emulations, or FPGA systemsAutomation of processes to reduce human error and improve ease of use with greater control-abilityHold Masters in Signal ProcessingCertification in Project ManagementASIC designASIC VerificationEmulation VerificationSpecialties: Block and System Environment development, Emulation VerificationHands-on Verification Methodologies like OVM, RVM, VMM, and UVMHands-on Emulation verification on Palladium platformsSystem-level verification for SoCs, ASICs, Multi-Chip Simulation/EmulationHands-on usage of ARM Mxs, MIPS, and SoC bring upClock Generation Design in a complete SoCHands-on System Verilog, Verilog, VHDL, VERA, Specman

Listed skills include Verilog, Asic, Functional Verification, Soc, and 30 others.