- Part of a team building an AI inference Accelerator based on In-Memory Compute and Chiplet level scalability for LLMs- Carried out the verification of PCIe-Gen5 Subsystem and over SoC- Verified different features targeting application of chip- Worked on coverage closure for Sub-system verification- Verified Different data-paths for single and multi chiplets- Leading a team of 25+ engineers to carry out different VIPs such as (Memory Protocols, USB and eDP)

- Spearheaded the establishment of a new engineering team in Vietnam, growing it to over 15+ engineers.- Trained the team to successfully deliver complex projects, including HBM3, LPDDR5, and USB3

- Part of a team building an AI inference Accelerator based on In-Memory Compute and Chiplet level scalability for LLMs- Completely developed and owned the Verification plan, UVM testbench and coverage- Created the Testbench from scratch for verification of LPDDR5 Memory subsystem in Chiplet based environment- Verified several features and closed the coverage for Memory subsystem- Created the generic testbench for different flavors of SDRAM to reduce verification effort-… Show more - Part of a team building an AI inference Accelerator based on In-Memory Compute and Chiplet level scalability for LLMs- Completely developed and owned the Verification plan, UVM testbench and coverage- Created the Testbench from scratch for verification of LPDDR5 Memory subsystem in Chiplet based environment- Verified several features and closed the coverage for Memory subsystem- Created the generic testbench for different flavors of SDRAM to reduce verification effort- Lead the team of 10+  DV Engineers to develop in-house Memory VIP such as DDR5 (LRDIMM) and LPDDR5.x Show less

- Building test bench to support different features of RISC-V core - Creating the test plan for FPU, DTM and PLIC unit - Writing coverage to ensure the perfect verification- Creating the VIPs from scratch for the blocks mentioned above

- Worked on different memory protocols such as DDR3/4, LPDDR3/4, GDDR5 and SD card- Created the Test bench that includes multiples VIPs such as AHB, APB and AXI that was needed to configure and help in data transfer- Building the test plan, check plan and coverage plan for effective verification and project closure - Coding the Performance Monitor to find out the Utilization numbers and the latencies for enhancing the DUTs Performance- Providing 24 x 7 support to clients

HEP trainee at the Mentor Graphics, Noida for 8 weeks. Learned Verilog, System Verilog and basics of UVM.