- Explored gm over ID Methodology for Analog Circuit Design: Researched and understood the gm over ID methodology, analyzed the gm to ID ratio for MOSFET devices, and applied it to optimize analog circuit performance. Implemented layout design with compliance to DRC and LVS verification, validating designs through simulation across Process, Voltage, and Temperature (PVT) variations, along with Monte Carlo simulation for process mismatch.- Designed CMOS Inverter, NAND Gate, and NOR Gate: Utilized transistor-level design techniques to meet performance criteria, optimized for speed, power consumption, and noise margins. Translate schematic designs into physical layouts adhering to DRC and LVS standards, validating performance through simulation across PVT variations and Monte Carlo simulation for process mismatch.- Performed Prelayout and PostLayout Simulation: Conducted preliminary simulations using schematic netlists, performed post-layout simulations considering layout-dependent effects, and validated performance across PVT variations. Ensure layout modifications adhere to DRC and LVS constraints, and validate layouts through Monte Carlo simulation for process mismatch.- Designed Telescopic Structure of OTA: Defined OTA specifications, design OTA architecture using MOSFET devices, optimize transistor sizing and biasing schemes, implemented layout design with verification adherence to DRC and LVS requirements, and validated OTA performance through simulation across PVT variations and Monte Carlo simulation for process mismatch.- Design and Verification of Reference VDAC for LVDS VCM. applied skills to design, and validate VDAC performance across PVT variations and Monte Carlo simulation for process mismatch.Technology - STMI IMG140 - 65nm, 180 nm