Software Engineer
CurrentVerific Design Automation Inc. develops and sells source code (C++) Verilog, SystemVerilog, and VHDL front-ends (parsers, ana-lyzers, elaborators) as well as a generic hierarchical netlist database for EDA applications.Many EDA and semiconductor companies worldwide are shipping products incorporating Verific's Verilog and VHDL technology, with a combined customer base of over 40,000 users. Applications include RTL simulation, FPGA synthesis, Model Checking, Functional Verification… Show more Verific Design Automation Inc. develops and sells source code (C++) Verilog, SystemVerilog, and VHDL front-ends (parsers, ana-lyzers, elaborators) as well as a generic hierarchical netlist database for EDA applications.Many EDA and semiconductor companies worldwide are shipping products incorporating Verific's Verilog and VHDL technology, with a combined customer base of over 40,000 users. Applications include RTL simulation, FPGA synthesis, Model Checking, Functional Verification, Hardware Acceleration, RTL Debug, Logic Equivalence Checking, RTL Floorplanning, HDL Entry, and Design for Test. I am part of the team to develop analyzer and elaborator. One of my major contribution is to develop elaboration in mixed language flow and support of system verilog class synthesis.I am also the person behind developing efficient synthesis algorithms to synthesize SVA to RTL. In this flow Verific converts a assertion to a synthesizable RTL logic. www.verific.com Show less
