Sanjeev Bagga Email & Phone Number

I specialise in Field Applications support of complex devices for use in Enterprise Storage Systems (SAS/SATA, FC, PCIe).I spent 25 years in ASIC/FPGA design and as a general Hardware Design Engineer. Excelled in design and delivery of complex digital boards. Enjoyed design process from specification through implementation, the tackling and resolution of problems, to sign-off of fully tested products. Experienced team leader who effectively coached and co-ordinated team members, but was equally capable of being an effective team member.Specialties: Verilog, SystemVerilog, Mentor HDL Designer with CVS, Syplify, ModelSim/Questasim.Xilinx ISE, Altera Quartus and Lattice ISP Lever.Extensive knowledge of telecommunications including carrier grade Ethernet using double tagged VLANs, ATM, SDH, PDH, synchronisation (including packet) and jitter.Working knowledge of many interface protocols (inc STMn, GigE, PCIe, I2C, SPI-3, Utopia).Linux, basic PERL scripting, basic TCL scripting.

Listed skills include Fpga, Asic, Verilog, and Systemverilog.

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  University Of Bradford

  Electronic Engineering