Saravanan Baskaran Email & Phone Number

Sunnyvale, Ca, Us

San Jose, California, Us

Responsible for overseeing the day-to-day engineering activities and managing the FPGA RTL design verification, Emulation, and system-validation teams, establishing technical requirements, project scope development, building engineering teams, workflow coordination, IP vendor selection, and staff evaluation.During my tenure at Infinera, I have worked as an Architect, Sr Manager, Team Lead, Individual Contributor, and have been responsible for the successful shipment of 6 ASICs AND 9 FPGAs as part of six generations of the product line. - Led the FPGA vendor selection process and IP vendor - Lead a team of RTL design and verification in developing FPGAs - Coordination with HW team for pin-out, power, and SerDes characterization - Established Jenkins based continuous integration process for the FPGA development cycle - Responsible for delivering tested ASIC/FPGA and SDK - Responsible for developing the Unified Validation Platform to ensure multi-product readiness - Defined the post-silicon and System-level validation plan in collaboration with system architect and Software QA - Collaborating with system architects to identify and reviewed full-chip and system-level test-plan - Established HW-SW Hybrid Emulation methodology using Synopsys Zebu ZS4 emulation platform - Working with the SDK team in defining service and debug APIs - Working with EDA vendors to explore the latest verification methodology and its usefulness for Infinera's ASICs/FPGAs - Working with product planning and system architecture team in developing chip level architecture and micro-architecture - Developed ADC/DAC and SerDes characterization framework to characterize ASICs for Long-haul, Sub-sea, and Metro application - Architect and defined UVM based verification methodology, process, and infrastructure for sub-chip and full chip pre-silicon verification

Dallas, Tx, Us

Santa Clara, California, Us

In INTEL, I was working for ESO (Ethernet Switching Operation) ESO develops chipset for L2+ and L3 switching and routing platform. I was involved in the verification of different flow control and drop algorithms

Bangalore, Karnataka, In

Design of Hardware, Signal Integrity, ASIC Verification of telecom System/ASIC for Customer projects

Bachelor Of Engineering, Electrical & Electronics

Education record

Education record